Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.8. Native PHY IP Ports for PIPE

Figure 108. Signals and Ports of Native PHY IP for PIPE


Table 191.   Ports for Arria 10 Transceiver Native PHY in PIPE ModeThis section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter settings.
Port Direction Clock Domain Description
Clocks
rx_cdr_refclk0 In N/A The 100/125 MHz input reference clock source for the PHY's TX PLL and RX CDR.
tx_serial_clk0/tx_serial_clk1 In N/A The high speed serial clock generated by the PLL.

Note: For Gen3 x1 ONLY tx_serial_clk1 is used.

pipe_hclk_in[0] In N/A The 500 MHz clock used for the ASN block. This clock is generated by the PLL, configured for Gen1/Gen2.

Note: For Gen3 designs, use from the fPLL that is used for Gen1/Gen2.

pipe_hclk_out[0] Out N/A The 500 MHz clock output provided to the PHY - MAC interface. The