Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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Document Table of Contents

2.7.8. Native PHY IP Ports for PIPE

Figure 108. Signals and Ports of Native PHY IP for PIPE


Table 191.   Ports for Arria 10 Transceiver Native PHY in PIPE ModeThis section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter settings.
Port Direction Clock Domain Description
Clocks
rx_cdr_refclk0 In N/A The 100/125 MHz input reference clock source for the PHY's TX PLL and RX CDR.
tx_serial_clk0/tx_serial_clk1 In N/A The high speed serial clock generated by the PLL.

Note: For Gen3 x1 ONLY tx_serial_clk1 is used.

pipe_hclk_in[0] In N/A The 500 MHz clock used for the ASN block. This clock is generated by the PLL, configured for Gen1/Gen2.

Note: For Gen3 designs, use from the fPLL that is used for Gen1/Gen2.

pipe_hclk_out[0] Out N/A The 500 MHz clock output provided to the PHY - MAC interface. The pipe_hclk_out [0] port can be left floating when you connect tx_clkout to the MAC clock input.
PIPE Input from PHY - MAC Layer
tx_parallel_data[31:0], [15:0], or [7:0] In

tx_coreclkin

The TX parallel data driven from the MAC. For Gen1 this can be 8 or 16 bits. For Gen2 this is 16 bits. For Gen3 this is 32 bits.

Note: unused_tx_parallel_data should be tied to '0'.

Active High. Refer to table Bit Mappings when the Simplified Interface is Disabled for additional details.

tx_datak[3:0], [1:0], or [0] In

tx_coreclkin

The data and control indicator for the transmitted data.

For Gen1 or Gen2, when 0, indicates that tx_parallel_data is data, when 1, indicates that tx_parallel_data is control.

For Gen3, bit[0] corresponds to tx_parallel_data[7:0], bit[1] corresponds to tx_parallel_data[15:8], and so on.

Active High. Refer to table Bit Mappings when the Simplified Interface is Disabled for additional details.

pipe_tx_sync_hdr[(2N-1):0] 44 In

tx_coreclkin

For Gen3, indicates whether the 130-bit block transmitted is a Data or Control Ordered Set Block.

The following encodings are defined:

2'b10: Data block

2'b01: Control Ordered Set Block

This value is read when pipe_tx_blk_start = 1b'1.

Refer to Lane Level Encoding in the PCI Express* Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.

Not used for Gen1 and Gen2 data rates.

Active High

pipe_tx_blk_start[(N-1):0] In

tx_coreclkin

For Gen3, specifies the start block byte location for TX data in the 128-bit block data. Used when the interface between the PCS and PHY-MAC (FPGA Core) is 32 bits.

Not used for Gen1 and Gen2 data rates.

Active High

pipe_tx_elecidle[(4N-1):0] In

Asynchronous

Forces the transmit output to electrical idle. Refer to the Intel® PHY Interface for PCI Express (PIPE) for timing diagrams.

Gen1 - Width of signal is 1 bit/lane.

Gen2 - Width of signal is 2 bits/lane. For example, if the MAC connected to PIPE Gen2x4 has 1bit/lane, then you can use the following mapping to connect to PIPE: {pipe_tx_elecidle[7:0] = {{2{tx_elecidle_ch3}},{2{tx_elecidle_ch2}},{2{tx_elecidle_ch1}},{2{tx_elecidle_ch0}}} where tx_elecidle_* is the output signal from MAC.

Gen3 - Width of signal is 4 bits/lane. For example, if the MAC connected to PIPE Gen3x4 has 1bit/lane, then you can use the following mapping to connect to PIPE: {pipe_tx_elecidle[15:0] = {{4{tx_elecidle_ch3}},{4{tx_elecidle_ch2}},{4{tx_elecidle_ch1}},{4{tx_elecidle_ch0}}} where tx_elecidle_* is the output signal from MAC.

Active High

pipe_tx_detectrx_loopback [(N-1):0] In

tx_coreclkin

Instructs the PHY to start a receive detection operation. After power-up, asserting this signal starts a loopback operation. Refer to section 6.4 of the Intel® PHY Interface for PCI Express (PIPE) for a timing diagram.

Active High

pipe_tx_compliance[(4N-1):0] In

tx_coreclkin

Asserted for one cycle to set the running disparity to negative. Used when transmitting the compliance pattern. Refer to section 6.11 of the Intel® PHY Interface for PCI Express (PIPE) Architecture for more information.

Gen1 - Width of signal is 1 bit/lane.

Gen2 - Width of signal is 2 bits/lane.

For example, if the MAC connected to PIPE Gen2x4 has 1bit/lane, then you can use the following mapping to connect to PIPE:{pipe_tx_compliance[7:0] = {{2{tx_compliance_ch3}}, {2{tx_compliance _ch2}},{2{tx_compliance_ch1}}, {2{tx_compliance _ch0}}}. Where tx_compliance_* is the output signal from MAC.

Gen3 - Width of signal is 4 bits/lane.

For example, if the MAC connected to PIPE Gen3x4 has 1bit/lane, then you can use the following mapping to connect to PIPE: {pipe_tx_compliance[15:0]= {{4{tx_ compliance _ch3}}, {4{tx_ compliance _ch2}}, {4{tx_ compliance _ch1}}, {4{tx_ compliance _ch0}}}. Where tx_ compliance _* is the output signal from MAC.

Active High

pipe_rx_polarity[(N-1):0] In

Asynchronous

When 1'b1, instructs the PHY layer to invert the polarity on the received data.

Active High

pipe_powerdown[(2N-1):0] In

tx_coreclkin

Requests the PHY to change its power state to the specified state. The Power States are encoded as follows:

2'b00: P0 - Normal operation.

2'b01: P0s - Low recovery time, power saving state.

2'b10: P1 - Longer recovery time, lower power state .

2'b11: P2 - Lowest power state.

pipe_tx_margin[(3N-1):0] In

tx_coreclkin

Transmit VOD margin selection. The PHY-MAC sets the value for this signal based on the value from the Link Control 2 Register. The following encodings are defined:

3'b000: Normal operating range

3'b001: Full swing: 800 - 1200 mV; Half swing: 400 - 700 mV.

3'b010:-3'b011: Reserved.

3'b100-3'b111: Full swing: 200 - 400mV; Half swing: 100 - 200 mV else reserved.

pipe_tx_swing[(N-1):0] In

tx_coreclkin

Indicates whether the transceiver is using Full swing or Half swing voltage as defined by the pipe_tx_margin.

1'b0-Full swing.

1'b1-Half swing.

pipe_tx_deemph[(N-1):0] In

Asynchronous

Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it selects the transmitter de-emphasis:

1'b0: –6 dB.

1'b1: –3.5 dB.

pipe_g3_tx_deemph[(18N-1):0] In

Asynchronous

The pipe_g3_tx_deemph port is used to select the link partners transmitter de-emphasis during equalization. The 18 bits specify the following coefficients:

[5:0]: C-1

[11:6]: C0

[17:12]: C+1

Refer to Preset Mappings to TX De-emphasis for presets to TX de-emphasis mappings. In Gen3 capable designs, the TX de-emphasis for Gen2 data rate is always -6 dB. The TX de-emphasis for Gen1 data rate is always -3.5 dB.

Refer to section 6.6 of Intel® PHY Interface for PCI Express (PIPE) Architecture for more information.

Note: Intel® recommends transmitting Preset P8 coefficients for Arria® 10 receiver to recover data successfully.
pipe_g3_rxpresethint[(3N-1):0] In

Asynchronous

This is used to trigger CTLE adaptation in Phase2 (EP) /Phase 3 (RP) to achieve receiver Bit Error Rate (BER) that is less than 10-12.

Gen3 capable design at Gen1/Gen2 speeds: This should be set to 3’b000.

Gen3 capable design at Gen3 speed: Refer to section “PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate” for details on when to set/reset this port.

pipe_rx_eidleinfersel[(3N-1):0] In

Asynchronous

When asserted high, the electrical idle state is inferred instead of being identified using analog circuitry to detect a device at the other end of the link. The following encodings are defined:

3'b0xx: Electrical Idle Inference not required in current LTSSM state.

3'b100: Absence of COM/SKP OS in 128 ms.

3'b101: Absence of TS1/TS2 OS in 1280 UI interval for Gen1 or Gen2.

3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2.

3'b111: Absence of Electrical Idle exit in 128 ms window for Gen1.

Note: Recommended to implement Receiver Electrical Idle Inference (EII) in FPGA fabric.
pipe_rate[1:0] In

Asynchronous

The 2-bit encodings defined in the following list:

2'b00: Gen1 rate (2.5 Gbps)

2'b01: Gen2 rate (5.0 Gbps)

2'b10: Gen3 rate (8.0 Gbps)

pipe_sw_done[1:0] In

N/A

Signal from the Master clock generation buffer, indicating that the rate switch has completed. Use this signal for bonding mode only.

For non-bonded applications, this signal is internally connected to the local CGB.

pipe_tx_data_valid[(N-1):0] In

tx_coreclkin

For Gen3, this signal is deasserted by the MAC to instruct the PHY to ignore tx_parallel_data for current clock cycle. A value of 1'b1 indicates the PHY should use the data. A value of 0 indicates the PHY should not use the data.

Active High

PIPE Output to PHY - MAC Layer
rx_parallel_data[31:0], [15:0], or [7:0] Out

rx_coreclkin

The RX parallel data driven to the MAC.

For Gen1 this can be 8 or 16 bits. For Gen2 this is 16 bits only. For Gen3 this is 32 bits.Refer to Bit Mappings When the Simplified Interface is Disabled for more details.

rx_datak[3:0], [1:0], or [0] Out

rx_coreclkin

The data and control indicator.

For Gen1 or Gen2, when 0, indicates that rx_parallel_data is data, when 1, indicates that rx_parallel_data is control.

For Gen3, Bit[0] corresponds to rx_parallel_data[7:0], Bit[1] corresponds to rx_parallel_data[15:8], and so on. Refer to tableBit Mappings When the Simplified Interface is Disabled for more details.

pipe_rx_sync_hdr[(2N-1):0] Out

rx_coreclkin

For Gen3, indicates whether the 130-bit block being transmitted is a Data or Control Ordered Set Block. The following encodings are defined:

2'b10: Data block

2'b01: Control Ordered Set block

This value is read when pipe_rx_blk_start = 4'b0001. Refer to Section 4.2.2.1. Lane Level Encoding in the PCI Express Base Specification, Rev. 3.0 for a detailed explanation of data transmission and reception using 128b/130b encoding and decoding.

pipe_rx_blk_start[(N-1):0] Out

rx_coreclkin

For Gen3, specifies the start block byte location for RX data in the 128-bit block data. Used when the interface between the PCS and PHY-MAC (FPGA Core) is 32 bits. Not used for Gen1 and Gen2 data rates.

Active High

pipe_rx_data_valid[(N-1):0] Out

rx_coreclkin

For Gen3, this signal is deasserted by the PHY to instruct the MAC to ignore rx_parallel_data for current clock cycle. A value of 1'b1 indicates the MAC should use the data. A value of 1'b0 indicates the MAC should not use the data.

Active High

pipe_rx_valid[(N-1):0] Out

rx_coreclkin

Asserted when RX data and control are valid.
pipe_phy_status[(N-1):0] Out

rx_coreclkin

Signal used to communicate completion of several PHY requests.

Active High

pipe_rx_elecidle[(N-1):0] Out

Asynchronous

When asserted, the receiver has detected an electrical idle.

Active High

pipe_rx_status[(3N-1):0] Out

rx_coreclkin

Signal encodes receive status and error codes for the receive data stream and receiver detection. The following encodings are defined:

3'b000 - Receive data OK

3'b001 - 1 SKP added

3'b010 - 1 SKP removed

3'b011 - Receiver detected

3'b100 - Either 8B/10B or 128b/130b decode error and (optionally) RX disparity error

3'b101 - Elastic buffer overflow

3'b110 - Elastic buffer underflow

3'b111 - Receive disparity error, not used if disparity error is reported using 3'b100.

pipe_sw[1:0] Out N/A Signal to clock generation buffer indicating the rate switch request. Use this signal for bonding mode only.

For non-bonded applications this signal is internally connected to the local CGB.

Active High. Refer to Bit Mappings When the Simplified Interface Is Disabled Bit Mappings When the Simplified Interface is Disabled for more details.

Table 192.  Bit Mappings When the Simplified Interface Is DisabledThis section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Signal Name Gen1 (TX Byte Serializer and RX Byte Deserializer disabled) Gen1 (TX Byte Serializer and RX Byte Deserializer in X2 mode), Gen2 (TX Byte Serializer and RX Byte Deserializer in X2 mode) Gen3
tx_parallel_data tx_parallel_data[7:0] tx_parallel_data[29:22,7:0] tx_parallel_data[40:33,29:22,18:11,7:0]
tx_datak tx_parallel_data[8] tx_parallel_data[30,8] tx_parallel_data[41,30,19,8]
pipe_tx_compliance tx_parallel_data[9] tx_parallel_data[31,9] tx_parallel_data[42,31,20,9]
pipe_tx_elecidle tx_parallel_data[10] tx_parallel_data[32,10] tx_parallel_data[43,32,21,10]
pipe_tx_detectrx_loopbacK tx_parallel_data[46] tx_parallel_data[46] tx_parallel_data[46]
pipe_powerdown tx_parallel_data[48:47] tx_parallel_data[48:47] tx_parallel_data[48:47]
pipe_tx_margin tx_parallel_data[51:49] tx_parallel_data[51:49] tx_parallel_data[51:49]
pipe_tx_swing tx_parallel_data[53] tx_parallel_data[53] tx_parallel_data[53]
rx_parallel_data rx_parallel_data[7:0] rx_parallel_data[39:32,7:0] rx_parallel_data[55:48,39:32,23:16,7:0]
rx_datak rx_parallel_data[8] rx_parallel_data[40,8] rx_parallel_data[56,40,24,8]
rx_syncstatus rx_parallel_data[10] rx_parallel_data[42,10] rx_parallel_data[58,42,26,10]
pipe_phy_status rx_parallel_data[65] rx_parallel_data[65] rx_parallel_data[65]
pipe_rx_valid rx_parallel_data[66] rx_parallel_data[66] rx_parallel_data[66]
pipe_rx_status rx_parallel_data[69:67] rx_parallel_data[69:67] rx_parallel_data[69:67]
pipe_tx_deemph N/A tx_parallel_data[52] N/A
pipe_tx_sync_hdr N/A N/A tx_parallel_data[55:54]
pipe_tx_blk_start N/A N/A tx_parallel_data[56]
pipe_tx_data_valid N/A N/A tx_parallel_data[60]
pipe_rx_sync_hdr N/A N/A rx_parallel_data[71:70]
pipe_rx_blk_start N/A N/A rx_parallel_data[72]
pipe_rx_data_valid N/A N/A rx_parallel_data[76]
Refer to section 6.6 of Intel® PHY Interface for PCI Express (PIPE) Architecture for more information.
44 N is the number of PCIe* channels.

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