Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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4.3.2.2. Resetting the Transmitter During Device Operation

The numbers in this list correspond to the numbers in the following figure.
  1. Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while pll_cal_busy and tx_cal_busy are low.
  2. Wait for tx_analogreset_ack to go high, to ensure successful assertion of tx_analogreset. tx_analogreset_ack goes high when TRS has successfully completed the reset request for assertion. After both pll_locked and tx_analogreset_ack are asserted, deassert tx_analogreset. This step can be done at the same time or after you deassert pll_powerdown.
  3. Wait for tx_analogreset_ack to go low, to ensure successful deassertion of tx_analogreset. tx_analogreset_ack goes low when TRS has successfully completed the reset request for deassertion.
  4. The pll_locked signal goes high after the TX PLL acquires lock. Wait for tx_analogreset_ack to go low before monitoring the pll_locked signal.
  5. Deassert tx_digitalreset a minimum ttx_digitalreset time after pll_locked goes high.
Figure 212. Transmitter Reset Sequence During Device Operation

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