Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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5.2.1.1.4. Basic Mode

In Basic mode, the TX Core FIFO operates as an elastic buffer, where buffer depths can vary. This mode allows driving write and read side of TX Core FIFO with different clock frequencies. Monitor the FIFO flag to control write and read operations. For TX Core FIFO, assert tx_fifo_wr_en with tx_fifo_pempty signal going low.

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