Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.3. Configuration Files

The Arria® 10 Transceiver Native PHY and Transmit PLL IP cores optionally allow you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance.

The configuration files are generated during IP generation. They are located in the <IP instance name>\altera_xcvr_<IP type>_a10_<quartus version>\synth\reconfig subfolder of the IP instance. The configuration data is available in the following formats:

  • SystemVerilog packages: <name>.sv
  • C Header files: <name>.h
  • Memory Initialization File (MIF): <name>.mif

Select one or more of the configuration file formats on the Dynamic Reconfiguration tab of the Transceiver Native PHY or Transmit PLL parameter editor to store the configuration data. All configuration files generated for a particular IP instance contain the same address and data values. The contents of the configuration files can be used to reconfigure from one transceiver /PLL configuration to another.

You can optionally allow the Native PHY IP core to include PMA Analog settings in the configuration files by enabling the feature Include PMA Analog settings in configuration files in the Dynamic Reconfirmation tab of the Transceiver Native PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds the PMA analog settings specified in the Analog PMA settings (Optional) tab of the Native PHY IP Parameter Editor to the configuration files. Even with this option enabled in the Native PHY IP Parameter Editor, you must still specify Quartus Settings File (QSF) assignments for your analog settings when compiling your static design. The analog settings selected in the Native PHY IP Parameter Editor are used only to include these settings and their dependent settings in the selected configuration files. Refer to the Analog Parameter Settings chapter for details about QSF assignments for the analog settings.

SystemVerilog Configuration File

    26'h008FF04, 	
// [25:16]-DPRIO address=0x008;
// [15:8]-bit mask=0xFF; 
// [7:7]- hssi_tx_pcs_pma_interface_pldif_datawidth_mode=pldif_data_10bit(1'h0); 
// [6:5]-hssi_tx_pcs_pma_interface_tx_pma_data_sel=ten_g_pcs(2'h0); 
// [4:4]-hssi_tx_pcs_pma_interface_prbs_gen_pat=prbs_gen_dis(1'h0); 
// [3:0]-hssi_tx_pcs_pma_interface_sq_wave_num=sq_wave_default(4'h4);
…

localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_VALUE = "pldif_data_10bit";
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_OFST = 8;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_OFST = 7;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_HIGH = 7;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_SIZE = 1;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MO