Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

3.1.2.2. ATX PLL IP Core

Table 229.  ATX PLL Configuration Options, Parameters, and Settings
Parameter Range Description

Message level for rule violations

Error

Warning

Specifies the messaging level to use for parameter rule violations.

  • Error—Causes all rule violations to prevent IP generation.
  • Warning—Displays all rule violations as warnings and allows IP generation in spite of violations.

Protocol mode

Basic

PCIe* Gen1

PCIe Gen2

PCIe Gen3

SDI_cascade

OTN_cascade

UPI TX

SAS TX

Governs the internal setting rules for the VCO.

This parameter is not a preset. You must set all other parameters for your protocol.

Bandwidth

Low

Medium

High

Specifies the VCO bandwidth.

Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.

Number of PLL reference clocks

1 to 5

Specifies the number of input reference clocks for the ATX PLL.

You can use this parameter for data rate reconfiguration.

Selected reference clock source

0 to 4

Specifies the initially selected reference clock input to the ATX PLL.

Primary PLL clock output buffer

 GX clock output buffer

GT clock output buffer

Specifies which PLL output is active initially.

  • If GX is selected, turn ON "Enable PLL GX clock output port".
  • If GT is selected, turn ON “Enable PLL GT clock output port".
Enable PLL GX clock output port 52

On/Off 

Enables the GX output port which feeds x1 clock lines.

You must select this parameter for PLL output frequency less than 8.7 GHz, or if you intend to reconfigure the PLL to a frequency below 8.7 GHz.

Turn ON this port if GX is selected in the "Primary PLL clock output buffer".

Enable PCIe clock output port 

 On/Off

Exposes the pll_pcie_clk port used for PCI Express*.

The port should be connected to the pipe_hclk_input port.

Enable ATX to FPLL cascade clock output port

 On/Off

Enables the ATX to FPLL cascade clock output port.

Enable fref and clklow port 53.

 On/Off

Enables fref and clklow ports for external lock detector.

PLL output frequency

Refer to Intel® Arria® 10 Device Datasheet .

Use this parameter to specify the target output frequency for the PLL.

PLL integer reference clock frequency

Refer to the GUI

Selects the input reference clock frequency for the PLL.

Multiply factor (M-Counter)

Read only

For OTN_cascade or SDI_cascade, refer to the GUI.

Displays the M-counter value.

Specifies the M-counter value (In SDI_cascade or OTN_cascade Protocol mode only).

Divide factor (N-Counter)   

Read only

For SDI_cascade or OTN_cascade, refer to the GUI.

Displays the N-counter value.

For SDI_cascade or OTN_cascade, refer to the GUI.

Divide factor (L-Counter) 

Read only

Displays the L-counter value.

Predivide factor (L-Cascade Predivider)

Refer to the GUI

Specifies the L-cascade predivider value. This value must be 2 for a VCO frequency greater than 10.46 GHz and 1 for a VCO frequency less than 10.46GHz. (In SDI_cascade or OTN_cascade Protocol mode only).

Fractional multiply factor (K)

Read only

Displays the actual K-counter value. This parameter is only available in fractional mode.

Table 230.  ATX PLL—Master Clock Generation Block Parameters and Settings
Parameter Range Description

Include Master Clock Generation Block 54

On/Off

When enabled, includes a master CGB as a part of the ATX PLL IP core. The PLL output drives the Master CGB.

This is used for x6/xN bonded and non-bonded modes.

Clock division factor

 1, 2, 4, 8

Divides the master CGB clock input before generating bonding clocks.

Enable x6/xN non-bonded high-speed clock output port

 On/Off

Enables the master CGB serial clock output port used for x6/xN non-bonded modes.

Enable PCIe clock switch interface

 On/Off

Enables the control signals for the PCIe clock switch circuitry. Used for PCIe clock rate switching.

Number of auxiliary MCGB clock input ports

0, 1

Auxiliary input is used to implement the PCIe Gen3 protocol.

MCGB input clock frequency

Read only

Displays the master CGB's input clock frequency.

MCGB output data rate.

Read only

Displays the master CGB's output data rate.

Enable bonding clock output ports

On/Off

Enables the tx_bonding_clocks output ports of the master CGB used for channel bonding.

This option should be turned ON for bonded designs.

Enable feedback compensation bonding

On/Off

Enables this setting when using feedback compensation bonding. For more details about feedback compensation bonding, refer to the PLL Feedback Compensation Bonding section later in the document.

PMA interface width

8, 10, 16, 20, 32, 40, 64

Specifies PMA-PCS interface width.

Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.

Table 231.  ATX PLL—Dynamic Reconfiguration
Parameter Range Description

Enable reconfiguration

On/Off

Enables the PLL reconfiguration interface. Enables the simulation models and adds Avalon® compliant ports for reconfiguration.

Enable Native PHY Debug Master Endpoint

On/Off

When you turn on this option, the Transceiver PLL IP core includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for more details.

Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE

On/Off

When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. (Only available if "Enable control and status registers feature" is enabled).

Enable capability registers

On/Off

Enables capability registers that provide high-level information about the ATX PLL's configuration.

Set user-defined IP identifier

User-defined

Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.

Enable control and status registers

On/Off

Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic.

Configuration file prefix

Enter the prefix name for the configuration files to be generated.

Generate SystemVerilog package file 

On/Off

Generates a SystemVerilog package file containing all relevant parameters used by the PLL.

Generate C header file

On/Off

Generates a C header file containing all relevant parameters used by the PLL.

Enable multiple reconfiguration profiles

On/Off

Enables multiple configuration profiles to be stored.

Enable embedded reconfiguration streamer

On/Off

Enables embedded reconfiguration streamer which automates the dynamic reconfiguration process between multiple predefined configuration profiles.

Generate reduced reconfiguration files

On/Off

When enabled, the IP generates reconfiguration report files containing only the setting differences between the multiple reconfiguration profiles

Number of reconfiguration profiles

1 to 8

Specifies the number of reconfiguration profiles

Store current configuration to profile

0 to 7

Specifies which configuration profile to modify (store, load, clear or refresh) when clicking the corresponding action button.

Generate MIF (Memory Initialize File)

On/Off

Generates a MIF file which contains the current configuration.

Use this option for reconfiguration purposes in order to switch between different PLL configurations.

Table 232.  ATX PLL—Generation Options
Parameter Range Description

Generate parameter documentation file

On/Off

Generates a .csv file which contains descriptions of ATX PLL IP core parameters and values.

Table 233.  ATX PLL IP Core Ports
Port Direction Clock Domain Description

pll_powerdown

Input

Asynchronous

Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel FPGA IP).

pll_refclk0

Input

N/A

Reference clock input port 0.

There are a total of five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

pll_refclk1

Input

N/A

Reference clock input port 1.

pll_refclk2

Input

N/A

Reference clock input port 2.

pll_refclk3

Input

N/A

Reference clock input port 3.

pll_refclk4

Input

N/A

Reference clock input port 4.

tx_serial_clk

Output

N/A

High speed serial clock output port for GX channels. Represents the x1 clock network.

tx_serial_clk_gt

Output

N/A

High speed serial clock output port for GT channels. Represents the GT clock network.

pll_locked

Output

Asynchronous

Active high status signal which indicates if the PLL is locked.

pll_pcie_clk

Output

N/A

Used for PCIe. 55

reconfig_clk0

Input

N/A

Optional Avalon® interface clock. Used for PLL reconfiguration. The reconfiguration ports appear only if the Enable Reconfiguration parameter is selected in the PLL IP Core GUI. When this parameter is not selected, the ports are set to OFF internally.

reconfig_reset0

Input

reconfig_clk0

Used to reset the Avalon® interface. Asynchronous to assertion and synchronous to deassertion.

reconfig_write0

Input

reconfig_clk0

Active high write enable signal.

reconfig_read0

Input

reconfig_clk0

Active high read enable signal.

reconfig_address0[9:0]

Input

reconfig_clk0

10-bit address bus used to specify address to be accessed for both read and write operations.

reconfig_writedata0[31:0]

Input

reconfig_clk0

32-bit data bus. Carries the write data to the specified address.

reconfig_readdata0[31:0]

Output

reconfig_clk0

32-bit data bus. Carries the read data from the specified address.

reconfig_waitrequest0

Output

reconfig_clk0

Indicates when the Avalon® interface signal is busy. When asserted, all inputs must be held constant.

pll_cal_busy

Output

Asynchronous

Status signal which is asserted high when PLL calibration is in progress.

OR this signal with tx_cal_busy port before connecting to the reset controller IP.

mcgb_rst

Input

Asynchronous

Master CGB reset control.

Deassert this reset at the same time as pll_powerdown .

mcgb_aux_clk0

Input

N/A

Used for PCIe implementation to switch between fPLL and ATX PLL during link speed negotiation.

tx_bonding_clocks[5:0]

Output

N/A

Optional 6-bit bus which carries the low speed parallel clock outputs from the master CGB. Each transceiver channel in a bonded group has this 6-bit bus.

Used for channel bonding, and represents the x6/xN clock network.

mcgb_serial_clk

Output

N/A

High speed serial clock output for x6/xN non-bonded configurations.

pcie_sw[1:0]

Input

Asynchronous

2-bit rate switch control input used for PCIe protocol implementation.

pcie_sw_done[1:0]

Output

Asynchronous

2-bit rate switch status output used for PCIe protocol implementation.

atx_to_fpll_cascade_clk

Output

N/A

The ATX PLL output clock is used to drive fPLL reference clock input (only available in SDI_cascade or OTN_cascade protocol mode).

ext_lock_detect_clklow 56

Output

N/A

Clklow output for external lock detection. It can be exposed by selecting the Enable clklow and fref port

ext_lock_detect_fref 56

Output

N/A

Fref output for external lock detection. It can be exposed by selecting the Enable clklow and fref port.
52 You can enable both the GX clock output port and the GT clock output port. However, only one port can be in operation at any given time. You can switch between the two ports using PLL reconfiguration.
53 The fPLL fref and clklow signals should only be used with the Intel® external soft lock detection logic.
54 Manually enable the MCGB for bonding applications.
55 Connect this clock to hclk in PCIe applications.
56 The fPLL fref and clklow signals should only be used with the Intel® external soft lock detection logic.

Did you find the information on this page useful?

Characters remaining:

Feedback Message