Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

3.1.2.2. ATX PLL IP Core

Table 229.  ATX PLL Configuration Options, Parameters, and Settings
Parameter Range Description

Message level for rule violations

Error

Warning

Specifies the messaging level to use for parameter rule violations.

  • Error—Causes all rule violations to prevent IP generation.
  • Warning—Displays all rule violations as warnings and allows IP generation in spite of violations.

Protocol mode

Basic

PCIe* Gen1

PCIe Gen2

SAS TX

Governs the internal setting rules for the VCO.

This parameter is not a preset. You must set all other parameters for your protocol.

Bandwidth

Low

Medium

High

Specifies the VCO bandwidth.

Higher bandwidth reduces PLL lock time, at the expense of decreased