126.96.36.199. Byte Deserializer
The byte deserializer allows the transceiver to operate at data rates higher than those supported by the FPGA fabric. It deserializes the recovered data by multiplying the data width two or four times, depending upon the deserialization mode selected. The byte deserializer is optional in designs that do not exceed the FPGA fabric interface frequency upper limit. You can bypass the byte deserializer by disabling it in the Quartus® Prime Transceiver Native PHY. The byte deserializer operates in disabled, deserialize x2, or deserialize x4 modes.
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