Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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4.5. Using a User-Coded Reset Controller

You can design your own user-coded reset controller instead of using Transceiver PHY Reset Controller. Your user-coded reset controller must provide the following functionality for the recommended reset sequence:
  • A clock signal input for your reset logic
  • Holds the transceiver channels in reset by asserting the appropriate reset control signals
  • Checks the PLL status (for example, checks the status of pll_locked and pll_cal_busy)
Note: You must ensure a stable reference clock is present at the PLL transmitter before releasing pll_powerdown.

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