Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

2.6.4.7. Avalon® Memory-Mapped Interface Registers

The Avalon® memory-mapped interface slave signals provide access to all registers.
Table 143.   Avalon® Memory-Mapped Interface Signals
Signal Name Direction Clock Domain Description
mgmt_clk Input Clock The clock signal that controls the Avalon® memory-mapped interface PHY management. If you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you m