Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents Avalon® Memory-Mapped Interface Registers

The Avalon® memory-mapped interface slave signals provide access to all registers.
Table 143.   Avalon® Memory-Mapped Interface Signals
Signal Name Direction Clock Domain Description
mgmt_clk Input Clock The clock signal that controls the Avalon® memory-mapped interface PHY management. If you plan to use the same clock for the PHY management interface and transceiver reconfiguration, you must restrict the frequency to 100-125 MHz to meet the specification for the transceiver reconfiguration clock.
mgmt_clk_reset Input Asynchronous reset Resets the PHY management interface. This signal is active high and level sensitive.
mgmt_addr[10:0] Input Synchronous to mgmt_clk 11-bit Avalon® memory-mapped interface address.
mgmt_writedata[31:0] Input Synchronous to mgmt_clk Input data.
mgmt_readdata[31:0] Output Synchronous to mgmt_clk Output data.
mgmt_write Input Synchronous to mgmt_clk Write signal. Active high.
mgmt_read Input Synchronous to mgmt_clk Read signal. Active high.
mgmt_waitrequest Output Synchronous to mgmt_clk When asserted, indicates that the Avalon® memory-mapped interface slave is unable to respond to a read or write request. When asserted, control signals to the Avalon® memory-mapped interface slave must remain constant.

Did you find the information on this page useful?

Characters remaining:

Feedback Message