Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

1.1.1. Arria® 10 GX Device Transceiver Layout

The largest Arria® 10 GX device includes 96 transceiver channels. A column array of eight transceiver banks on the left and the right side periphery of the device is shown in the following figure. Each transceiver bank has six transceiver channels. Some devices have transceiver banks with only three channels. The transceiver banks with only three channels are the uppermost transceiver banks. Arria® 10 devices also include PCI Express* Hard IP blocks.

The figures below illustrate different transceiver bank layouts for Arria® 10 GX device variants.

For more information about PCIe* Hard IP transceiver placements, refer to Related Information at the end of this section.

Figure 2.  Arria® 10 GX Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks
Figure 3.  Arria® 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard IP Blocks.
Figure 4.  Arria® 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP Blocks
Figure 5.  Arria® 10 GX Devices with 48, 36, and 24 Transceiver Channels and Two PCIe Hard IP Blocks
Figure 6.  Arria® 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP Block
Figure 7.  Arria® 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block


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