Intel® Arria® 10 Transceiver PHY User Guide

Download
ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.9.2.11. How to Enable Low Latency in Basic

In the Arria® 10 Transceiver Native PHY IP Parameter Editor, use the following settings to enable low latency:

  1. Select the Enable 'Standard PCS' low latency mode option.
  2. Select either low_latency or register FIFO in the TX FIFO mode list.
  3. Select either low_latency or register FIFO in the RX FIFO mode list.
  4. Select either Disabled or Serialize x2 in the TX byte serializer mode list.
  5. Select either Disabled or Serialize x2 in the RX byte deserializer mode list.
  6. Ensure that RX rate match FIFO mode is disabled.
  7. Set the RX word aligner mode to bitslip.
  8. Set the RX word aligner pattern length to 7 or 16.
    Note: TX bitslip, RX bitslip, bit reversal, and polarity inversion modes are supported.

Did you find the information on this page useful?

Characters remaining:

Feedback Message