Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.2.2.6. CDR Control

The CDR control block performs the following functions:
  • Controls the PMA CDR to obtain bit and symbol alignment
  • Controls the PMA CDR to deskew within the allocated time
  • Generates status signals for other PCS blocks
The PCIe* base specification requires that the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates. The transceivers have an improved CDR control block to accommodate fast lock times. Fast lock times are necessary for the CDR to relock to the new multiplier/divider settings when entering or exiting Gen3 speeds.

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