Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration

Transceiver Clocking

Figure 87. Transceiver Clocking for XAUI Configuration Without Phase Compensation FIFO EnabledThe external ATX PLL generates the transmitter serial and parallel clocks for the four XAUI channels. You must instantiate the PLL and connect it to XAUI. The x6 clock line carries the transmitter serial and parallel clocks to the PMA and PCS of each of the four channels.

Note: When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel. This ensures that the serial clock is running at 3.125 Gbps while the input reference clock is 156.25 MHz.
Figure 88. Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO EnabledWhen phase compensation FIFO is enabled, you can connect the core to different clocks on the Avalon-ST interface.

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