Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

2.4.8. PMA Ports

This section describes the PMA and calibration ports for the Arria® 10 Transceiver Native PHY IP core.

The following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <d>—The serialization factor
  • <s>—The symbol size
  • <p>—The number of PLLs
Table 44.  TX PMA Ports
Name Direction Clock Domain Description
tx_serial_data[<n>-1:0] Input N/A

This is the serial data output of the TX PMA.

tx_serial_clk0 Input Clock This is the serial clock from the TX PLL. The frequency of this clock depends on the data rate and clock division factor. This clock is for non bonded channels only. For bonded channels use the tx_bonding_clocks clock TX input.
tx_bonding_clocks[<n><6>-1:0] Input Clock This is a 6-bit bus which carries the low speed parallel clock per channel. These clocks are outputs from the master CGB. Use these clocks for bonded channels only.
Optional Ports