Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.4.8. PMA Ports

This section describes the PMA and calibration ports for the Arria® 10 Transceiver Native PHY IP core.

The following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <d>—The serialization factor
  • <s>—The symbol size
  • <p>—The number of PLLs
Table 44.  TX PMA Ports
Name Direction Clock Domain Description
tx_serial_data[<n>-1:0] Input N/A

This is the serial data output of the TX PMA.

tx_serial_clk0 Input Clock This is the serial clock from the TX PLL. The frequency of this clock depends on the data rate and clock division factor. This clock is for non bonded channels only. For bonded channels use the tx_bonding_clocks clock TX input.
tx_bonding_clocks[<n><6>-1:0] Input Clock This is a 6-bit bus which carries the low speed parallel clock per channel. These clocks are outputs from the master CGB. Use these clocks for bonded channels only.
Optional Ports
tx_serial_clk1

tx_serial_clk2

tx_serial_clk3

tx_serial_clk4

Inputs Clocks

These are the serial clocks from the TX PLL. The frequency of these clocks depends on the data rate and clock division factor. These additional ports are enabled when you specify more than one TX PLL.

tx_analog_reset_ack Output Asynchronous Enables the optional tx_pma_analog_reset_ack output. This port should not be used for register mode data transfers
tx_pma_clkout[<n>-1:0] Output Clock This clock is the low speed parallel clock from the TX PMA. It is available when you turn on Enable tx_pma_clkout port in the Transceiver Native PHY IP core Parameter Editor. 33
tx_pma_div_clkout[<n>-1:0] Output Clock If you specify a tx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a tx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the TX FIFO runs at a different rate than the PMA parallel clock frequency, such as 66:40 applications.
tx_pma_iqtxrx_clkout Output Clock This port is available if you turn on Enable tx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the TX PMA output clock to the input of a PLL.
tx_pma_elecidle[<n>-1:0] Input Asynchronous When you assert this signal, the transmitter is forced to electrical idle. This port has no effect when you configure the transceiver for the PCI Express* protocol.
tx_pma_qpipullup[<n>-1:0] Input Asynchronous This port is available if you turn on Enable tx_pma_qpipullup port (QPI) in the Transceiver Native PHY IP core Parameter Editor. It is only used for Quick Path Interconnect (QPI) applications.
tx_pma_qpipulldn[<n>-1:0] Input Asynchronous This port is available if you turn on Enable tx_pma_qpipulldn port (QPI) in the Transceiver Native PHY IP core Parameter Editor. It is only used for Quick Path Interconnect (QPI) applications.
tx_pma_txdetectrx[<n>-1:0] Input Asynchronous This port is available if you turn on Enable tx_pma_txdetectrx port (QPI) in the Transceiver Native PHY IP core Parameter Editor. When asserted, the receiver detect block in TX PMA detects the presence of a receiver at the other end of the channel. After receiving the tx_pma_txdetectrx request, the receiver detect block initiates the detection process. Use this port for Quick Path Interconnect (QPI) applications only.
tx_pma_rxfound[<n>-1:0] Output

Synchronous to rx_coreclkin or rx_clkout based on the configuration.

This port is available if you turn on Enable tx_rxfound_pma port (QPI) in the Transceiver Native PHY IP core Parameter Editor. When asserted, indicates that the receiver detect block in TX PMA has detected a receiver at the other end of the channel. Use this port for Quick Path Interconnect (QPI) applications only.
rx_seriallpbken[<n>-1:0] Input Asynchronous This port is available if you turn on Enable rx_seriallpbken port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal can be enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.
Table 45.  RX PMA Ports
Name Direction Clock Domain Description
rx_serial_data[<n>-1:0] Input N/A

Specifies serial data input to the RX PMA.

rx_cdr_refclk0 Input Clock

Specifies reference clock input to the RX clock data recovery (CDR) circuitry.

Optional Ports
rx_cdr_refclk1rx_cdr_refclk4 Input Clock

Specifies reference clock inputs to the RX clock data recovery (CDR) circuitry.

rx_analog_reset_ack Output Asynchronous Enables the optional rx_pma_analog_reset_ack output. This port should not be used for register mode data transfers.
rx_pma_clkout[<n>-1:0] Output Clock

This clock is the recovered parallel clock from the RX CDR circuitry.

rx_pma_div_clkout[<n>-1:0] Output Clock The deserializer generates this clock. This is used to drive core logic, PCS-to-FPGA fabric interface, or both. If you specify a rx_pma_div_clkout division factor of 1 or 2, this clock output is derived from the PMA parallel clock (low speed parallel clock). If you specify a rx_pma_div_clkout division factor of 33, 40, or 66, this clock is derived from the PMA serial clock. This clock is commonly used when the interface to the RX FIFO runs at a different rate than the PMA parallel clock (low speed parallel clock) frequency, such as 66:40 applications.
rx_pma_iqtxrx_clkout Output Clock This port is available if you turn on Enable rx_ pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL.
rx_pma_clkslip Output Clock

When asserted, indicates that the deserializer has either skipped one serial bit or paused the serial clock for one cycle to achieve word alignment. As a result, the period of the parallel clock could be extended by 1 unit interval (UI) during the clock slip operation.

rx_pma_qpipulldn[<n>-1:0] Input Asynchronous

This port is only used for Quick Path Interconnect (QPI) applications.

rx_is_lockedtodata[<n>-1:0] Output rx_clkout

When asserted, indicates that the CDR PLL is locked to the incoming data, rx_serial_data.

rx_is_lockedtoref[<n>-1:0] Output rx_clkout

When asserted, indicates that the CDR PLL is locked to the input reference clock.

rx_set_locktodata[<n>-1:0] Input Asynchronous

This port provides manual control of the RX CDR circuitry.

rx_set_locktoref[<n>-1:0] Input Asynchronous

This port provides manual control of the RX CDR circuitry.

rx_seriallpbken[<n>-1:0] Input Asynchronous

This port is available if you turn on Enable rx_ seriallpbken port in the Transceiver Native PHY IP core Parameter Editor. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This signal is enabled in Duplex or Simplex mode. If enabled in Simplex mode, you must drive the signal on both the TX and RX instances from the same source. Otherwise the design fails compilation.

rx_prbs_done[<n>-1:0] Output rx_coreclkin or rx_clkout

When asserted, indicates the verifier has aligned and captured consecutive PRBS patterns and the first pass through a polynomial is complete.

rx_prbs_err[<n>-1:0] Output rx_coreclkin or rx_clkout

When asserted, indicates an error only after the rx_prbs_done signal has been asserted. This signal gets asserted for three parallel clock cycles for every error that occurs. Errors can only occur once per word.

rx_prbs_err_clr[<n>-1:0] Input rx_coreclkin or rx_clkout When asserted, clears the PRBS pattern and deasserts the rx_prbs_done signal.
Table 46.  Calibration Status Ports
Name Direction Clock Domain Description
tx_cal_busy[<n>-1:0] Output Asynchronous When asserted, indicates that the initial TX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed. You must hold the channel in reset until calibration completes.
rx_cal_busy[<n>-1:0] Output Asynchronous When asserted, indicates that the initial RX calibration is in progress. For both initial and manual recalibration, this signal is asserted during calibration and deasserts after calibration is completed.
Table 47.  Reset Ports
Name Direction Clock Domain34 Description
tx_analogreset[<n>-1:0] Input Asynchronous Resets the analog TX portion of the transceiver PHY.
tx_digitalreset[<n>-1:0] Input Asynchronous Resets the digital TX portion of the transceiver PHY.
rx_analogreset[<n>-1:0] Input Asynchronous Resets the analog RX portion of the transceiver PHY.
rx_digitalreset[<n>-1:0] Input Asynchronous Resets the digital RX portion of the transceiver PHY.
33 This clock is not to be used to clock the FPGA - transceiver interface. This clock may be used as a reference clock to an external clock cleaner.
34 Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock.

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