Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.5.2.1. Parameter Settings

You customize the PHY IP core by specifying the parameters in the parameter editor in the Intel® Quartus® Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 154.  Multi-rate Ethernet PHY IP Core Parameters

Name

Value

Description

Speed

2.5G

1G/2.5G

1G/2.5G/10G

10M/100M/1G/2.5G/5G/10G

The operating speed of the PHY.
Enable IEEE 1588 Precision Time Protocol On, Off

Select this option for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature.

This option is enabled only for 2.5G and 1G/2.5G.

Connect to MGBASE-T PHY On, Off

Select this option when the external PHY is MGBASE-T compatible.

This parameter is enabled for 2.5G, 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) modes.

Connect to NBASE-T PHY On, Off

Select this option when the external PHY is NBASE-T compatible.

This parameter is enabled for 10M/100M/1G/2.5G/5G/10G (USXGMII) modes.

PHY ID (32 bit) 32-bit value

An optional 32-bit unique identifier:

  • Bits 3 to 24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE
  • 6-bit model number
  • 4-bit revision number

If unused, do not change the default value, which is 0x00000000.

Reference clock frequency for 10 GbE (MHz) 322.265625, 644.53125 Specify the frequency of the reference clock for 10GbE.
Selected TX PMA local clock division factor for 1 GbE 1, 2, 4, 8 This parameter is the local clock division factor in the 1G mode. It is directly mapped to the Native PHY IP Core GUI options.
Selected TX PMA local clock division factor for 2.5 GbE 1, 2 This parameter is the local clock division factor in the 2.5G mode. It is directly mapped to the Native PHY IP Core GUI options.
Enable Native PHY Debug Master Endpoint (NPDME) On, Off Available in Native PHY and TX PLL IP parameter editors. When enabled, the Native PHY Debug Master Endpoint (NPDME) is instantiated and has access to the Avalon® memory-mapped interface of the Native PHY. You can access certain test and debug functions using System Console with the NPDME. Refer to the Embedded Debug Features section for more details about NPDME.
Enable capability registers On, Off Available in Native PHY and TX PLL IP parameter editors. Enables capability registers. These registers provide high-level information about the transceiver channel's/PLL's configuration.
Set user-defined IP identifier User-specified Available in Native PHY and TX PLL IP parameter editors. Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On, Off Available in Native PHY and TX PLL IP parameter editors. Enables soft registers for reading status signals and writing control signals on the PHY/PLL interface through the NPDME or reconfiguration interface.
Enable PRBS soft accumulators On, Off Available in Native PHY IP parameter editor only. Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.

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