Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.6.4. GMII Interface

The GMII interface signals drive data to and from the PHY.

Table 138.  GMII Interface Ports
Signal Name Direction Description
gmii_tx_d[7:0] Input Data to be encoded and sent to the link partner. This signal is clocked with tx_clkout.
gmii_tx_en Input The GMII TX control signal. Synchronous to tx_clkout.
gmii_tx_err Input The GMII TX error signal. Synchronous to tx_clkout.
gmii_rx_d[7:0] Output Data to be encoded and sent to the link partner. This signal is clocked with tx_clkout.
gmii_rx_dv Output The GMII RX control signal. Synchronous to tx_clkout.
gmii_rx_err Output The GMII RX error signal. Synchronous to tx_clkout.
led_char_err Output 10-bit character error. Asserted for one rx_clkout_1g cycle when an erroneous 10-bit character is detected.
led_link Output When asserted, this signal indicates successful link synchronization.
led_disp_err Output When asserted, this signal indicates a 10-bit running disparity error. Asserted for one rx_clkout_1g cycle when a disparity error is detected. A running disparity error indicates that errors were detected on more received groups than the previous and possibly current groups.
led_an Output This signal indicates the auto-negotiation status. The PCS function asserts this signal when an auto-negotiation completes.

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