Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

3.11.3. Implementing PLL Cascading

In PLL cascading, the output of the first PLL feeds the input reference clock to the second PLL.

For example, if the input reference clock has a fixed frequency, and the desired data rate was not an integer multiple of the input reference clock, the first PLL can be used to generate the correct reference clock frequency. This output is fed as the input reference clock to the second PLL. The second PLL generates the clock frequency required for the desired data rate.

The transceivers in Arria® 10 devices support fPLL to fPLL cascading. For OTN and SDI applications, there is a dedicated clock path for cascading ATX PLL to fPLL in Arria 10 production silicon. Only maximum two PLLs are allowed in the cascading chain.
Note: When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.
Figure 199. PLL Cascading

Steps to implement fPLL to fPLL cascading:

  1. Instantiate the fPLL IP core. Refer to