Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents 10GBASE-KR Functional Description

The following figure shows the supporting components inside the 10GBASE-KR PHY IP core.

Figure 68. 10GBASE-KR PHY IP Core Block Diagram
Note: The 10GBASE-KR PHY IP core does not support backplane applications with IEEE 1588 Precision Time Protocol.

The 10GBASE-KR PHY IP core includes the following components:

Standard and Enhanced PCS Datapaths

The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more details on how these blocks support 1G, 10G protocols and FEC.

Auto Negotiation, IEEE 802.3 Clause 73

The auto negotiation (AN) is needed to synchronize the start time of the link training on both sides of the link partners. This ensures that the link training can be done effectively within the 500 ms of the specified time frame as required.

Link Training (LT), IEEE 802.3 Clause 72

Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72 standard training procedure. This IP includes:

  • training frame lock that is different from the regular 64b/66b frame_lock
  • training frame generation
  • the control channel codec
  • Local Device (LD) coefficient update
  • Link Partner (LP) coefficient generation

Reconfiguration Block

The Reconfiguration Block performs Avalon® memory-mapped interface writes to the PHY for both PCS and PMA reconfiguration. The Avalon® memory-mapped interface master accepts requests from the PMA or PCS controller. It performs the Read-Modify-Write or Write commands on the Avalon® memory-mapped interface. The PCS controller receives rate change requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and PCS.

Eight compile-time configuration modes are supported. The configuration modes include one set of four with reference clock at 322 MHz and one set of four with reference clock at 644 MHz. Each set of four consists of all combinations of FEC sublayer on/off.

Figure 69. Reconfiguration Block Details

Did you find the information on this page useful?

Characters remaining:

Feedback Message