Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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6.2. Interacting with the Reconfiguration Interface

Each transceiver channel and PLL contains Avalon® memory-mapped interface reconfiguration. The reconfiguration interface provides direct access to the programmable space of each channel and PLL. Communication with the channel and PLL reconfiguration interface requires an Avalon® memory-mapped interface master. Because each channel and PLL has its own dedicated Avalon® memory-mapped interface, you can dynamically modify channels either concurrently or sequentially, depending on how the Avalon® memory-mapped interface master is connected to the Avalon® memory-mapped interface reconfiguration.
Figure 268. Reconfiguration Interface in Arria® 10 Transceiver IP Cores

A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL instances, a Native PHY IP core instance can specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a single reconfiguration interface across all channels to perform dynamic reconfiguration.

Avalon® memory-mapped interface masters interact with the reconfiguration interface by performing Avalon read and write operations to initiate dynamic reconfiguration of specific transceiver parameters. All read and write operations must comply with Avalon® memory-mapped interface specifications.

Figure 269. Top-Level Signals of the Reconfiguration Interface

The user-accessible Avalon® memory-mapped interface reconfiguration and PreSICE Avalon® memory-mapped interface share a single internal configuration bus. This bus is arbitrated to get access to the Avalon® memory-mapped interface of the channel or PLL. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.

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