6.2. Interacting with the Reconfiguration Interface
A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL instances, a Native PHY IP core instance can specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a single reconfiguration interface across all channels to perform dynamic reconfiguration.
Avalon® memory-mapped interface masters interact with the reconfiguration interface by performing Avalon read and write operations to initiate dynamic reconfiguration of specific transceiver parameters. All read and write operations must comply with Avalon® memory-mapped interface specifications.
The user-accessible Avalon® memory-mapped interface reconfiguration and PreSICE Avalon® memory-mapped interface share a single internal configuration bus. This bus is arbitrated to get access to the Avalon® memory-mapped interface of the channel or PLL. Refer to the Arbitration section for more details about requesting access to and returning control of the internal configuration bus from PreSICE.
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