Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Table 94.  General and Datapath ParametersThe first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath options to customize the transceiver.

Parameter

Range

Message level for rule violations

error, warning

Transceiver Configuration Rule

10GBASE-R

10GBASE-R 1588

10GBASE-R with KR FEC

Transceiver mode

TX / RX Duplex, TX Simplex, RX Simplex

Number of data channels

1 to 96

Data rate

10312.5 Mbps

Enable datapath and interface reconfiguration

Off

Enable simplified data interface

On

Off

Table 95.  TX PMA Parameters

Parameter

Range

TX channel bonding mode

Not bonded

TX local clock division factor

1, 2, 4, 8

Number of TX PLL clock inputs per channel

1, 2, 3, 4

Initial TX PLL clock input selection

0

Table 96.  RX PMA Parameters

Parameter

Range

Number of CDR reference clocks

1 to 5

Selected CDR reference clock

0 to 4

Selected CDR reference clock frequency 35

156.25 MHz, 322.265625 MHz, and 644.53125 MHz

PPM detector threshold

100, 300, 500, 1000
CTLE adaptation mode manual
DFE adaptation mode adaptation enabled, manual, disabled
Number of fixed DFE taps 3, 7, 11
Table 97.  Enhanced PCS Parameters

Parameter

Range

Enhanced PCS/PMA interface width

32, 40, 64

Note: 10GBASE-R with KR-FEC allows 64 only.

FPGA fabric/Enhanced PCS interface width

66

Enable Enhanced PCS low latency mode

On

Off

Enable RX/TX FIFO double-width mode

Off

TX FIFO mode

  • Phase Compensation (10GBASE-R and 10GBASE-R with KR FEC)
  • Register or Fast register (10GBASE-R with 1588)

TX FIFO partially full threshold

11

TX FIFO partially empty threshold

2

RX FIFO mode

  • 10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC)
  • Register (10GBASE-R with 1588)

RX FIFO partially full threshold

23

RX FIFO partially empty threshold

2
Table 98.  64B/66B Encoder and Decoder Parameters

Parameter

Range

Enable TX 64B/66B encoder

On

Enable RX 64B/66B decoder

On

Enable TX sync header error insertion

On

Off

Table 99.  Scrambler and Descrambler Parameters

Parameter

Range

Enable TX scrambler (10GBASE-R / Interlaken)

On

TX scrambler seed (10GBASE-R / Interlaken)

0x03ffffffffffffff

Enable RX descrambler (10GBASE-R / Interlaken)

On

Table 100.  Block Sync Parameters

Parameter

Range

Enable RX block synchronizer

On

Enable rx_enh_blk_lock port

On

Off

Table 101.  Gearbox Parameters

Parameter

Range

Enable TX data polarity inversion

On

Off

Enable RX data polarity inversion

On

Off

Table 102.  Dynamic Reconfiguration Parameters

Parameter

Range

Enable dynamic reconfiguration

On

Off

Share reconfiguration interface

On

Off

Enable Native PHY Debug Master Endpoint

On

Off

De-couple reconfig_waitrequest from calibration

On

Off

Table 103.  Configuration Files Parameters

Parameter

Range

Configuration file prefix

Generate SystemVerilog package file

On

Off

Generate C header file

On

Off

Generate MIF (Memory Initialization File)

On

Off

Table 104.  Generation Options Parameters

Parameter

Range

Generate parameter documentation file

On

Off

35 The CDR reference clock frequency depends on your design settings. Intel recommends that you verify the link datarates to ensure the CDR locking capability before production.

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