Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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4.5.1. User-Coded Reset Controller Signals

Refer to the signals in the following figure and table for implementation of a user-coded reset controller.
Figure 219. User-Coded Reset Controller, Transceiver PHY, and TX PLL Interaction


Table 250.  User-coded Reset Controller, Transceiver PHY, and TX PLL Signals

Signal Name

Direction

Description

pll_powerdown

Output

Resets the TX PLL when asserted high.

tx_analogreset

Output

Resets the TX PMA when asserted high.

tx_digitalreset

Output

Resets the TX PCS when asserted high.

rx_analogreset

Output

Resets the RX PMA when asserted high.

rx_digitalreset

Output

Resets the RX PCS when asserted high.

clock

Input

Clock signal for the user-coded reset controller. You can use the system clock without synchronizing it to the PHY parallel clock. The upper limit on the input clock frequency is the frequency achieved in timing closure.

pll_cal_busy

Input

A high on this signal indicates the PLL is being calibrated.

pll_locked

Input

A high on this signal indicates that the TX PLL is locked to the ref clock.

tx_cal_busy

Input

A high on this signal indicates that TX calibration is active. If you have multiple PLLs, you can OR their pll_cal_busy signals together.

rx_is_lockedtodata

Input

A high on this signal indicates that the RX CDR is in the lock-to-data (LTD) mode.

rx_cal_busy

Input

A high on this signal indicates that RX calibration is active.

rx_is_lockedtoref

Input

A high on this signal indicates that the RX CDR is in the lock-to-reference (LTR) mode. This signal may toggle or be deasserted when the CDR is in LTD mode.

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