Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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4.4. Using the Transceiver PHY Reset Controller

Transceiver PHY Reset Controller is a configurable IP core that resets transceivers mainly in response to PLL lock activity. You can use this IP core rather than creating your own user-coded reset controller. You can define a custom reset sequence for the IP core. You can also modify the IP cores's generated clear text Verilog HDL file to implement custom reset logic.

The Transceiver PHY Reset Controller handles all transceiver reset sequencing and supports the following options:

  • Separate or shared reset controls per channel in response to PLL lock activity
  • Separate controls for the TX and RX channels and PLLs
  • Synchronization of the reset inputs
  • Hysteresis for PLL locked status inputs
  • Configurable reset timing
  • Automatic or manual reset recovery mode in response to loss of PLL lock

You should create your own reset controller if the Transceiver PHY Reset Controller IP does not meet your requirements, especially when you require independent transceiver channel reset. The following figure illustrates the typical use of the Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the transmit PLL.

Figure 217. Transceiver PHY Reset Controller System Diagram


The Transceiver PHY Reset Controller IP core connects to the Transceiver PHY and the Transmit PLL. The Transceiver PHY Reset Controller IP core receives status from the Transceiver PHY and the Transmit PLL. Based on the status signals or the reset input, it generates TX and RX reset signals to the Transceiver PHY and TX PLL.

The tx_ready signal indicates whether the TX PMA exits the reset state, and if the TX PCS is ready to transmit data. The rx_ready signal indicates whether the RX PMA exits the reset state, and if the RX PCS is ready to receive data. You must monitor these signals to determine when the transmitter and receiver are out of the reset sequence.

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