Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

4.4. Using the Transceiver PHY Reset Controller

Transceiver PHY Reset Controller is a configurable IP core that resets transceivers mainly in response to PLL lock activity. You can use this IP core rather than creating your own user-coded reset controller. You can define a custom reset sequence for the IP core. You can also modify the IP cores's generated clear text Verilog HDL file to implement custom reset logic.

The Transceiver PHY Reset Controller handles all transceiver reset sequencing and supports the following options:

  • Separate or shared reset controls per channel in response to PLL lock activity
  • Separate controls for the TX and RX channels and PLLs
  • Synchronization of the reset inputs
  • Hysteresis for PLL locked status inputs
  • Configurable reset timing
  • Automatic or manual reset recovery mode in response to loss of PLL lock

You should create your own reset controller if the Transceiver PHY Reset Controller IP does not meet your requirements, especially when you require independent transceiver channel reset. T