Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS)

The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures reliable transfer of data and status signals. It compensates for the phase difference between the FPGA fabric clock and tx_clkout (the low-speed parallel clock). The TX FIFO has a depth of 8 and operates in low latency mode, register mode, and fast register mode.
Figure 255. TX FIFO Block Diagram


You can control the write port using tx_clkout or tx_coreclkin. Use the tx_clkout signal for a single channel and tx_coreclkin when using multiple channels. The TX FIFO is shared with PCIe Gen3 and Enhanced PCS data paths.

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