Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS)

The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures reliable transfer of data and status signals. It compensates for the phase difference between the FPGA fabric clock and tx_clkout (the low-speed parallel clock). The TX FIFO has a depth of 8 and operates in low latency mode, register mode, and fast register mode.
Figure 255. TX FIFO Block Diagram