Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

3.1.4. CMU PLL

The clock multiplier unit (CMU) PLL resides locally within each transceiver channel. The channel PLL's primary function is to recover the receiver clock and data in the transceiver channel. In this case the PLL is used in clock and data recovery (CDR) mode.

When the channel PLL of channels 1 or 4 is configured in the CMU mode, the channel PLL can drive the local clock generation block (CGB) of its own channel, then the channel cannot be used as a receiver.

The CMU PLL from transceiver channel 1 and channel 4 can also be used to drive other transceiver channels within the same transceiver bank. The CDR of channels 0, 2, 3, and 5 cannot be configured as a CMU PLL.

For datarates lower than 6 Gbps, the local CGB divider has to be engaged (TX local division factor in transceiver PHY IP under the TX PMA tab) .

Figure 172. CMU PLL Block Diagram

Input Reference Clock

The input reference clock for a CMU PLL can be sourced from either the reference clock network or a receiver input pin. The input reference clock is a differential signal. For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the CMU PLL as the input reference clock source.The input reference clock must be stable and free-running at device power-up for proper PLL operation. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available. Refer to the Calibration section for details about PLL calibration and the CLKUSR clock requirement.

Note: The CMU PLL calibration is clocked by the CLKUSR clock which must be stable and available for calibration to proceed. Refer to the Calibration section for more details about the CLKUSR clock.

Reference Clock Multiplexer (Refclk Mux)

The refclk mux selects the input reference clock to the PLL from the various reference clock sources available.

N Counter

The N counter divides the refclk mux's output. The N counter division helps lower the loop bandwidth or reduce the frequency to within the phase frequency detector's (PFD) operating range. Possible divide ratios are 1 (bypass), 2, 4, and 8.

Phase Frequency Detector (PFD)

The reference clock (refclk) signal at the output of the N counter block and the feedback clock (fbclk) signal at the output of the M counter block is supplied as an input to the PFD. The PFD output is proportional to the phase difference between the two inputs.