Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

3.1.4. CMU PLL

The clock multiplier unit (CMU) PLL resides locally within each transceiver channel. The channel PLL's primary function is to recover the receiver clock and data in the transceiver channel. In this case the PLL is used in clock and data recovery (CDR) mode.

When the channel PLL of channels 1 or 4 is configured in the CMU mode, the channel PLL can drive the local clock generation block (CGB) of its own channel, then the channel cannot be used as a receiver.

The CMU PLL from transceiver channel 1 and channel 4 can also be used to drive other transceiver channels within the same transceiver bank. The CDR of channels 0, 2, 3, and 5 cannot be configured as a CMU PLL.

For datarates lower than 6 Gbps, the local CGB divider has to be engaged (TX local division factor in transceiver PHY IP under the TX PMA tab) .

Figure 172. CMU PLL Block Diagram