Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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2.9.3.2. PLL and GT Transceiver Channel Clock Lines

The ATX PLL is used to provide the clock source for the GT transceiver channels. Each ATX PLL has two dedicated GT clock lines which connect the PLL directly to the GT transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and 4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest of the clock network for higher performance.

Figure 161. GT Channel Configuration


When both the channels 0 and 1 are configured as GT channels, they are driven by the same ATX PLL and have to be configured to run at the same data rates. This is also true for channels 3 and 4 when they are configured as GT channels.

Note:
  • GT channel bonding is not supported.
  • For optimum performance of GT channel, the reference clock of ATX PLL is recommended to be from a dedicated reference clock pin in the same bank.

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