Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Transceiver PHY Overview 2. Implementing Protocols in Arria 10 Transceivers 3. PLLs and Clock Networks 4. Resetting Transceiver Channels 5. Arria 10 Transceiver PHY Architecture 6. Reconfiguration Interface and Dynamic Reconfiguration 7. Calibration 8. Analog Parameter Settings 9. Debugging Transceiver Toolkit
1. Arria® 10 Transceiver PHY Overview x
1.1. Device Transceiver Layout 1.2. Transceiver PHY Architecture Overview 1.3. Calibration 1.4. Arria® 10 Transceiver PHY Overview Revision History
1.1. Device Transceiver Layout x
1.1.1. Arria® 10 GX Device Transceiver Layout 1.1.2. Arria® 10 GT Device Transceiver Layout 1.1.3. Arria® 10 GX and GT Device Package Details 1.1.4. Arria® 10 SX Device Transceiver Layout 1.1.5. Arria® 10 SX Device Package Details
1.2. Transceiver PHY Architecture Overview x
1.2.1. Transceiver Bank Architecture 1.2.2. PHY Layer Transceiver Components 1.2.3. Transceiver Phase-Locked Loops 1.2.4. Clock Generation Block (CGB)
1.2.2. PHY Layer Transceiver Components x
1.2.2.1. The GX Transceiver Channel 1.2.2.2. The GT Transceiver Channel
1.2.3. Transceiver Phase-Locked Loops x
1.2.3.1. Advanced Transmit (ATX) PLL 1.2.3.2. Fractional PLL (fPLL) 1.2.3.3. Channel PLL (CMU/CDR PLL)
2. Implementing Protocols in Arria 10 Transceivers x
2.1. Transceiver Design IP Blocks 2.2. Transceiver Design Flow 2.3. Arria® 10 Transceiver Protocols and PHY IP Support 2.4. Using the Arria® 10 Transceiver Native PHY IP Core 2.5. Interlaken 2.6. Ethernet 2.7. PCI Express* (PIPE) 2.8. CPRI 2.9. Other Protocols 2.10. Simulating the Transceiver Native PHY IP Core 2.11. Implementing Protocols in Arria® 10 Transceivers Revision History
2.2. Transceiver Design Flow x
2.2.1. Select and Instantiate the PHY IP Core 2.2.2. Configure the PHY IP Core 2.2.3. Generate the PHY IP Core 2.2.4. Select the PLL IP Core 2.2.5. Configure the PLL IP Core 2.2.6. Generate the PLL IP Core 2.2.7. Reset Controller 2.2.8. Create Reconfiguration Logic 2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller 2.2.10. Connect Datapath 2.2.11. Make Analog Parameter Settings 2.2.12. Compile the Design 2.2.13. Verify Design Functionality
2.4. Using the Arria® 10 Transceiver Native PHY IP Core x
2.4.1. Presets 2.4.2. General and Datapath Parameters 2.4.3. PMA Parameters 2.4.4. Enhanced PCS Parameters 2.4.5. Standard PCS Parameters 2.4.6. PCS Direct 2.4.7. Dynamic Reconfiguration Parameters 2.4.8. PMA Ports 2.4.9. Enhanced PCS Ports 2.4.10. Standard PCS Ports 2.4.11. IP Core File Locations 2.4.12. Unused Transceiver RX Channels 2.4.13. Unsupported Features
2.4.9. Enhanced PCS Ports x
2.4.9.1. Enhanced PCS TX and RX Control Ports
2.5. Interlaken x
2.5.1. Metaframe Format and Framing Layer Control Word 2.5.2. Interlaken Configuration Clocking and Bonding 2.5.3. How to Implement Interlaken in Arria 10 Transceivers 2.5.4. Design Example 2.5.5. Native PHY IP Parameter Settings for Interlaken
2.5.2. Interlaken Configuration Clocking and Bonding x
2.5.2.1. xN Clock Bonding Scenario 2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine x
2.5.2.2.1. TX FIFO Soft Bonding 2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine
2.6. Ethernet x
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants 2.6.3. 10GBASE-KR PHY IP Core 2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core 2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.6. XAUI PHY IP Core 2.6.7. Acronyms
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 x
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2 2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2 2.6.1.4. Rate Match FIFO for GbE 2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria® 10 Transceivers 2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 x
2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2
2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants x
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R 2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers 2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC 2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R x
2.6.2.1.1. TX FIFO and RX FIFO
2.6.3. 10GBASE-KR PHY IP Core x
2.6.3.1. 10GBASE-KR PHY Release Information 2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization 2.6.3.3. 10GBASE-KR Functional Description 2.6.3.4. Parameterizing the 10GBASE-KR PHY 2.6.3.5. 10GBASE-KR PHY Interfaces 2.6.3.6. Avalon® Memory-Mapped Interface Registers 2.6.3.7. Creating a 10GBASE-KR Design 2.6.3.8. Design Example 2.6.3.9. Simulation Support
2.6.3.4. Parameterizing the 10GBASE-KR PHY x
2.6.3.4.1. General Options 2.6.3.4.2. 10GBASE-R Parameters 2.6.3.4.3. 10GBASE-KR Auto-Negotiation and Link Training Parameters 2.6.3.4.4. 10GBASE-KR Optional Parameters 2.6.3.4.5. Speed Detection Parameters
2.6.3.5. 10GBASE-KR PHY Interfaces x
2.6.3.5.1. Clock and Reset Interfaces 2.6.3.5.2. Data Interfaces 2.6.3.5.3. XGMII Mapping to Standard SDR XGMII Data 2.6.3.5.4. Serial Data Interface 2.6.3.5.5. Control and Status Interfaces 2.6.3.5.6. Dynamic Reconfiguration Interface
2.6.3.6. Avalon® Memory-Mapped Interface Registers x
2.6.3.6.1. 10GBASE-KR PHY Register Definitions 2.6.3.6.2. Hard Transceiver PHY Registers 2.6.3.6.3. Enhanced PCS Registers 2.6.3.6.4. PMA Registers
2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core x
2.6.4.1. 1G/10GbE PHY Release Information 2.6.4.2. 1G/10GbE PHY Performance and Resource Utilization 2.6.4.3. 1G/10GbE PHY Functional Description 2.6.4.4. Clock and Reset Interfaces 2.6.4.5. Parameterizing the 1G/10GbE PHY 2.6.4.6. 1G/10GbE PHY Interfaces 2.6.4.7. Avalon® Memory-Mapped Interface Registers 2.6.4.8. Creating a 1G/10GbE Design 2.6.4.9. Design Guidelines 2.6.4.10. Channel Placement Guidelines 2.6.4.11. Design Example 2.6.4.12. Simulation Support 2.6.4.13. TimeQuest Timing Constraints
2.6.4.5. Parameterizing the 1G/10GbE PHY x
2.6.4.5.1. General Options 2.6.4.5.2. 10GBASE-R Parameters 2.6.4.5.3. 10M/100M/1Gb Ethernet Parameters 2.6.4.5.4. Speed Detection Parameters 2.6.4.5.5. PHY Analog Parameters
2.6.4.6. 1G/10GbE PHY Interfaces x
2.6.4.6.1. Clock and Reset Interfaces 2.6.4.6.2. Data Interfaces 2.6.4.6.3. XGMII Mapping to Standard SDR XGMII Data 2.6.4.6.4. GMII Interface 2.6.4.6.5. Serial Data Interface 2.6.4.6.6. Control and Status Interfaces 2.6.4.6.7. MII 2.6.4.6.8. Dynamic Reconfiguration Interface
2.6.4.7. Avalon® Memory-Mapped Interface Registers x
2.6.4.7.1. 1G/10GbE Register Definitions 2.6.4.7.2. Hard Transceiver PHY Registers 2.6.4.7.3. Enhanced PCS Registers 2.6.4.7.4. Arria 10 GMII PCS Registers 2.6.4.7.5. PMA Registers 2.6.4.7.6. Speed Change Summary
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.5.2. Using the IP Core 2.6.5.3. Functional Description 2.6.5.4. Configuration Registers 2.6.5.5. Interface Signals
2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.5.1.1. Features 2.6.5.1.2. Release Information 2.6.5.1.3. Device Family Support 2.6.5.1.4. Resource Utilization
2.6.5.2. Using the IP Core x
2.6.5.2.1. Parameter Settings
2.6.5.3. Functional Description x
2.6.5.3.1. Clocking and Reset Sequence 2.6.5.3.2. Timing Constraints 2.6.5.3.3. Switching Operation Speed
2.6.5.4. Configuration Registers x
2.6.5.4.1. Register Map 2.6.5.4.2. Configuration Registers
2.6.5.5. Interface Signals x
2.6.5.5.1. Clock and Reset Signals 2.6.5.5.2. Operating Mode and Speed Signals 2.6.5.5.3. GMII Signals 2.6.5.5.4. XGMII Signals 2.6.5.5.5. Status Signals 2.6.5.5.6. Serial Interface Signals 2.6.5.5.7. Transceiver Status and Reconfiguration Signals 2.6.5.5.8. Avalon® Memory-Mapped Interface Signals
2.6.6. XAUI PHY IP Core x
2.6.6.1. Transceiver Datapath in a XAUI Configuration 2.6.6.2. XAUI Supported Features 2.6.6.3. XAUI PHY Release Information 2.6.6.4. XAUI PHY Device Family Support 2.6.6.5. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration 2.6.6.6. XAUI PHY Performance and Resource Utilization 2.6.6.7. Parameterizing the XAUI PHY 2.6.6.8. XAUI PHY Ports 2.6.6.9. XAUI PHY Interfaces 2.6.6.10. XAUI PHY Register Interface and Register Descriptions 2.6.6.11. XAUI PHY Timing Analyzer SDC Constraint
2.6.6.7. Parameterizing the XAUI PHY x
2.6.6.7.1. XAUI PHY General Parameters 2.6.6.7.2. XAUI PHY Advanced Options Parameters
2.6.6.9. XAUI PHY Interfaces x
2.6.6.9.1. SDR XGMII TX Interface 2.6.6.9.2. SDR XGMII RX Interface 2.6.6.9.3. Transceiver Serial Data Interface 2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces 2.6.6.9.5. XAUI PHY PMA Channel Controller Interface 2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface
2.7. PCI Express* (PIPE) x
2.7.1. Transceiver Channel Datapath for PIPE 2.7.2. Supported PIPE Features 2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2.7.4. How to Implement PCI Express* (PIPE) in Arria 10 Transceivers 2.7.5. Native PHY IP Parameter Settings for PIPE 2.7.6. fPLL IP Parameter Core Settings for PIPE 2.7.7. ATX PLL IP Parameter Core Settings for PIPE 2.7.8. Native PHY IP Ports for PIPE 2.7.9. fPLL Ports for PIPE 2.7.10. ATX PLL Ports for PIPE 2.7.11. Preset Mappings to TX De-emphasis 2.7.12. How to Place Channels for PIPE Configurations 2.7.13. PHY IP Core for PCIe* (PIPE) Link Equalization for Gen3 Data Rate 2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration Interface to manually tune Arria® 10 PCIe designs (Hard IP(HIP) and PIPE) (For debug only)
2.7.2. Supported PIPE Features x
2.7.2.1. Gen1/Gen2 Features 2.7.2.2. Gen3 Features
2.7.2.1. Gen1/Gen2 Features x
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) 2.7.2.1.2. Transmitter Electrical Idle Generation 2.7.2.1.3. Power State Management 2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support 2.7.2.1.5. Receiver Status 2.7.2.1.6. Receiver Detection 2.7.2.1.7. Gen1 and Gen2 Clock Compensation 2.7.2.1.8. PCIe* Reverse Parallel Loopback
2.7.2.2. Gen3 Features x
2.7.2.2.1. Auto-Speed Negotiation 2.7.2.2.2. Rate Switch 2.7.2.2.3. Gen3 Transmitter Electrical Idle Generation 2.7.2.2.4. Gen3 Clock Compensation 2.7.2.2.5. Gen3 Power State Management 2.7.2.2.6. CDR Control 2.7.2.2.7. Gearbox
2.7.12. How to Place Channels for PIPE Configurations x
2.7.12.1. Master Channel in Bonded Configurations
2.8. CPRI x
2.8.1. Transceiver Channel Datapath and Clocking for CPRI 2.8.2. Supported Features for CPRI 2.8.3. Word Aligner in Manual Mode for CPRI 2.8.4. How to Implement CPRI in Arria® 10 Transceivers 2.8.5. Native PHY IP Parameter Settings for CPRI
2.8.1. Transceiver Channel Datapath and Clocking for CPRI x
2.8.1.1. TX PLL Selection for CPRI 2.8.1.2. Auto-Negotiation
2.8.2. Supported Features for CPRI x
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI x
2.8.2.1.1. Transmitter and Receiver Latency
2.9. Other Protocols x
2.9.1. Using the 'Basic (Enhanced PCS)' and 'Basic with KR FEC' Configurations of Enhanced PCS 2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS 2.9.3. Design Considerations for Implementing Arria 10 GT Channels 2.9.4. How to Implement PCS Direct Transceiver Configuration Rule
2.9.1. Using the 'Basic (Enhanced PCS)' and 'Basic with KR FEC' Configurations of Enhanced PCS x
2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules in Arria 10 Transceivers 2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC 2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS 2.9.1.4. Enhanced PCS FIFO Operation 2.9.1.5. TX Data Bitslip 2.9.1.6. TX Data Polarity Inversion 2.9.1.7. RX Data Bitslip 2.9.1.8. RX Data Polarity Inversion
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS x
2.9.2.1. Word Aligner Manual Mode 2.9.2.2. Word Aligner Synchronous State Machine Mode 2.9.2.3. RX Bit Slip 2.9.2.4. RX Polarity Inversion 2.9.2.5. RX Bit Reversal 2.9.2.6. RX Byte Reversal 2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode 2.9.2.8. Rate Match FIFO Basic (Double Width) Mode 2.9.2.9. 8B/10B Encoder and Decoder 2.9.2.10. 8B/10B TX Disparity Control 2.9.2.11. How to Enable Low Latency in Basic 2.9.2.12. TX Bit Slip 2.9.2.13. TX Polarity Inversion 2.9.2.14. TX Bit Reversal 2.9.2.15. TX Byte Reversal 2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Arria® 10 Transceivers 2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations
2.9.3. Design Considerations for Implementing Arria 10 GT Channels x
2.9.3.1. Transceiver PHY IP 2.9.3.2. PLL and GT Transceiver Channel Clock Lines 2.9.3.3. Reset Controller 2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low Latency Mode 2.9.3.5. Arria 10 GT Channel Usage
2.10. Simulating the Transceiver Native PHY IP Core x
2.10.1. NativeLink Simulation Flow 2.10.2. Scripting IP Simulation 2.10.3. Custom Simulation Flow
2.10.1. NativeLink Simulation Flow x
2.10.1.1. How to Use NativeLink to Specify a ModelSim* Simulation 2.10.1.2. How to Use NativeLink to Run a ModelSim* RTL Simulation 2.10.1.3. How to Use NativeLink to Specify Third-Party RTL Simulators
2.10.2. Scripting IP Simulation x
2.10.2.1. Generating a Combined Simulator Setup Script
2.10.3. Custom Simulation Flow x
2.10.3.1. How to Use the Simulation Library Compiler 2.10.3.2. Custom Simulation Scripts
3. PLLs and Clock Networks x
3.1. PLLs 3.2. Input Reference Clock Sources 3.3. Transmitter Clock Network 3.4. Clock Generation Block 3.5. FPGA Fabric-Transceiver Interface Clocking 3.6. Transmitter Data Path Interface Clocking 3.7. Receiver Data Path Interface Clocking 3.8. Unused/Idle Clock Line Requirements 3.9. Channel Bonding 3.10. PLL Feedback and Cascading Clock Network 3.11. Using PLLs and Clock Networks 3.12. PLLs and Clock Networks Revision History
3.1. PLLs x
3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs 3.1.2. ATX PLL 3.1.3. fPLL 3.1.4. CMU PLL
3.1.2. ATX PLL x
3.1.2.1. Instantiating the ATX PLL IP Core 3.1.2.2. ATX PLL IP Core
3.1.3. fPLL x
3.1.3.1. Instantiating the fPLL IP Core 3.1.3.2. fPLL IP Core
3.1.4. CMU PLL x
3.1.4.1. Instantiating CMU PLL IP Core 3.1.4.2. CMU PLL IP Core
3.2. Input Reference Clock Sources x
3.2.1. Dedicated Reference Clock Pins 3.2.2. Receiver Input Pins 3.2.3. PLL Cascading as an Input Reference Clock Source 3.2.4. Reference Clock Network 3.2.5. Global Clock or Core Clock as an Input Reference Clock
3.3. Transmitter Clock Network x
3.3.1. x1 Clock Lines 3.3.2. x6 Clock Lines 3.3.3. xN Clock Lines 3.3.4. GT Clock Lines
3.9. Channel Bonding x
3.9.1. PMA Bonding 3.9.2. PMA and PCS Bonding 3.9.3. PCS Bonding Channels Placement Restrictions 3.9.4. Selecting Channel Bonding Schemes 3.9.5. Skew Calculations
3.9.1. PMA Bonding x
3.9.1.1. x6/xN Bonding 3.9.1.2. PLL Feedback Compensation Bonding
3.11. Using PLLs and Clock Networks x
3.11.1. Non-bonded Configurations 3.11.2. Bonded Configurations 3.11.3. Implementing PLL Cascading 3.11.4. Mix and Match Example 3.11.5. Timing Closure Recommendations
3.11.1. Non-bonded Configurations x
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration 3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration 3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration
3.11.2. Bonded Configurations x
3.11.2.1. Implementing x6/xN Bonding Mode 3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
4. Resetting Transceiver Channels x
4.1. When Is Reset Required? 4.2. Transceiver PHY Implementation 4.3. How Do I Reset? 4.4. Using the Transceiver PHY Reset Controller 4.5. Using a User-Coded Reset Controller 4.6. Combining Status or PLL Lock Signals 4.7. Timing Constraints for Bonded PCS and PMA Channels 4.8. Resetting Transceiver Channels Revision History
4.3. How Do I Reset? x
4.3.1. Model 1: Default Model 4.3.2. Model 2: Acknowledgment Model 4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
4.3.1. Model 1: Default Model x
4.3.1.1. Recommended Reset Sequence 4.3.1.2. Resetting the Transmitter During Device Operation 4.3.1.3. Resetting the Receiver During Device Operation 4.3.1.4. Resetting the Transceiver Channel During Device Operation 4.3.1.5. Dynamic Reconfiguration of Channel Using the Default Model
4.3.2. Model 2: Acknowledgment Model x
4.3.2.1. Recommended Reset Sequence 4.3.2.2. Resetting the Transmitter During Device Operation 4.3.2.3. Resetting the Receiver During Device Operation 4.3.2.4. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment Model 4.3.2.5. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
4.4. Using the Transceiver PHY Reset Controller x
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP 4.4.2. Transceiver PHY Reset Controller Parameters 4.4.3. Transceiver PHY Reset Controller Interfaces 4.4.4. Transceiver PHY Reset Controller Resource Utilization
4.5. Using a User-Coded Reset Controller x
4.5.1. User-Coded Reset Controller Signals
5. Arria 10 Transceiver PHY Architecture x
5.1. Arria® 10 PMA Architecture 5.2. Arria 10 Enhanced PCS Architecture 5.3. Arria® 10 Standard PCS Architecture 5.4. Arria 10 PCI Express* Gen3 PCS Architecture 5.5. Arria® 10 Transceiver PHY Architecture Revision History
5.1. Arria® 10 PMA Architecture x
5.1.1. Transmitter 5.1.2. Serializer 5.1.3. Transmitter Buffer 5.1.4. Receiver 5.1.5. Receiver Buffer 5.1.6. Clock Data Recovery (CDR) Unit 5.1.7. Deserializer 5.1.8. Loopback
5.1.3. Transmitter Buffer x
5.1.3.1. High Speed Differential I/O 5.1.3.2. Programmable Output Differential Voltage 5.1.3.3. Programmable Pre-Emphasis 5.1.3.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation 5.1.3.5. Programmable Transmitter On-Chip Termination (OCT)
5.1.5. Receiver Buffer x
5.1.5.1. Programmable Common Mode Voltage (VCM) 5.1.5.2. Programmable Differential On-Chip Termination (OCT) 5.1.5.3. Signal Detector 5.1.5.4. Continuous Time Linear Equalization (CTLE) 5.1.5.5. Variable Gain Amplifier (VGA) 5.1.5.6. Decision Feedback Equalization (DFE) 5.1.5.7. How to Enable CTLE and DFE
5.1.6. Clock Data Recovery (CDR) Unit x
5.1.6.1. Lock-to-Reference Mode 5.1.6.2. Lock-to-Data Mode 5.1.6.3. CDR Lock Modes
5.2. Arria 10 Enhanced PCS Architecture x
5.2.1. Transmitter Datapath 5.2.2. Receiver Datapath
5.2.1. Transmitter Datapath x
5.2.1.1. Enhanced PCS TX FIFO 5.2.1.2. Interlaken Frame Generator 5.2.1.3. Interlaken CRC-32 Generator 5.2.1.4. 64B/66B Encoder and Transmitter State Machine (TX SM) 5.2.1.5. Pattern Generators 5.2.1.6. Scrambler 5.2.1.7. Interlaken Disparity Generator 5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion 5.2.1.9. KR FEC Blocks
5.2.1.1. Enhanced PCS TX FIFO x
5.2.1.1.1. Phase Compensation Mode 5.2.1.1.2. Register Mode 5.2.1.1.3. Interlaken Mode 5.2.1.1.4. Basic Mode
5.2.1.5. Pattern Generators x
5.2.1.5.1. PRBS Pattern Generator (Shared between Enhanced PCS and Standard PCS) 5.2.1.5.2. Pseudo-Random Pattern Generator
5.2.2. Receiver Datapath x
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion 5.2.2.2. Block Synchronizer 5.2.2.3. Interlaken Disparity Checker 5.2.2.4. Descrambler 5.2.2.5. Interlaken Frame Synchronizer 5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) 5.2.2.7. Pseudo Random Pattern Verifier 5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker 5.2.2.9. Interlaken CRC-32 Checker 5.2.2.10. Enhanced PCS RX FIFO 5.2.2.11. RX KR FEC Blocks
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) x
5.2.2.6.1. PRBS Checker
5.2.2.10. Enhanced PCS RX FIFO x
5.2.2.10.1. Phase Compensation Mode 5.2.2.10.2. Register Mode 5.2.2.10.3. Interlaken Mode 5.2.2.10.4. 10GBASE-R Mode 5.2.2.10.5. Basic Mode
5.3. Arria® 10 Standard PCS Architecture x
5.3.1. Transmitter Datapath 5.3.2. Receiver Datapath
5.3.1. Transmitter Datapath x
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) 5.3.1.2. Byte Serializer 5.3.1.3. 8B/10B Encoder 5.3.1.4. Polarity Inversion Feature 5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator 5.3.1.6. TX Bit Slip
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) x
5.3.1.1.1. TX FIFO Low Latency Mode 5.3.1.1.2. TX FIFO Register Mode 5.3.1.1.3. TX FIFO Fast Register Mode
5.3.1.2. Byte Serializer x
5.3.1.2.1. Bonded Byte Serializer 5.3.1.2.2. Byte Serializer Disabled Mode 5.3.1.2.3. Byte Serializer Serialize x2 Mode 5.3.1.2.4. Byte Serializer Serialize x4 Mode
5.3.1.3. 8B/10B Encoder x
5.3.1.3.1. 8B/10B Encoder Control Code Encoding 5.3.1.3.2. 8B/10B Encoder Reset Condition 5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature 5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature 5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature 5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
5.3.2. Receiver Datapath x
5.3.2.1. Word Aligner 5.3.2.2. RX Polarity Inversion Feature 5.3.2.3. Rate Match FIFO 5.3.2.4. 8B/10B Decoder 5.3.2.5. Pseudo-Random Binary Sequence (PRBS) Checker 5.3.2.6. Byte Deserializer 5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS)
5.3.2.1. Word Aligner x
5.3.2.1.1. Word Aligner Bit Slip Mode 5.3.2.1.2. Word Aligner Manual Mode 5.3.2.1.3. Word Aligner Synchronous State Machine Mode 5.3.2.1.4. Word Aligner Deterministic Latency Mode 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes 5.3.2.1.6. Word Aligner RX Bit Reversal Feature 5.3.2.1.7. Word Aligner RX Byte Reversal Feature
5.3.2.4. 8B/10B Decoder x
5.3.2.4.1. 8B/10B Decoder Control Code Encoding 5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
5.3.2.6. Byte Deserializer x
5.3.2.6.1. Byte Deserializer Disabled Mode 5.3.2.6.2. Byte Deserializer Deserialize x2 Mode 5.3.2.6.3. Byte Deserializer Deserialize x4 Mode 5.3.2.6.4. Bonded Byte Deserializer
5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) x
5.3.2.7.1. RX FIFO Low Latency Mode 5.3.2.7.2. RX FIFO Register Mode
5.4. Arria 10 PCI Express* Gen3 PCS Architecture x
5.4.1. Transmitter Datapath 5.4.2. Receiver Datapath 5.4.3. PIPE Interface
5.4.1. Transmitter Datapath x
5.4.1.1. TX FIFO (Shared with Standard and Enhanced PCS) 5.4.1.2. Gearbox
5.4.2. Receiver Datapath x
5.4.2.1. Block Synchronizer 5.4.2.2. Rate Match FIFO 5.4.2.3. RX FIFO (Shared with Standard and Enhanced PCS)
5.4.3. PIPE Interface x
5.4.3.1. Auto Speed Negotiation 5.4.3.2. Clock Data Recovery Control
6. Reconfiguration Interface and Dynamic Reconfiguration x
6.1. Reconfiguring Channel and PLL Blocks 6.2. Interacting with the Reconfiguration Interface 6.3. Configuration Files 6.4. Multiple Reconfiguration Profiles 6.5. Embedded Reconfiguration Streamer 6.6. Arbitration 6.7. Recommendations for Dynamic Reconfiguration 6.8. Steps to Perform Dynamic Reconfiguration 6.9. Direct Reconfiguration Flow 6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow 6.11. Reconfiguration Flow for Special Cases 6.12. Changing PMA Analog Parameters 6.13. Ports and Parameters 6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks 6.15. Embedded Debug Features 6.16. Using Data Pattern Generators and Checkers 6.17. Timing Closure Recommendations 6.18. Unsupported Features 6.19. Arria® 10 Transceiver Register Map 6.20. Reconfiguration Interface and Dynamic Revision History
6.2. Interacting with the Reconfiguration Interface x
6.2.1. Reading from the Reconfiguration Interface 6.2.2. Writing to the Reconfiguration Interface
6.11. Reconfiguration Flow for Special Cases x
6.11.1. Switching Transmitter PLL 6.11.2. Switching Reference Clocks
6.11.2. Switching Reference Clocks x
6.11.2.1. ATX Reference Clock Switching 6.11.2.2. fPLL Reference Clock Switching 6.11.2.3. CDR and CMU Reference Clock Switching
6.12. Changing PMA Analog Parameters x
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow 6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow 6.12.3. CTLE Settings in Triggered Adaptation Mode 6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow
6.15. Embedded Debug Features x
6.15.1. Native PHY Debug Master Endpoint 6.15.2. Optional Reconfiguration Logic
6.15.2. Optional Reconfiguration Logic x
6.15.2.1. Capability Registers 6.15.2.2. Control and Status Registers 6.15.2.3. PRBS Soft Accumulators
6.16. Using Data Pattern Generators and Checkers x
6.16.1. Using PRBS Data Pattern Generator and Checker 6.16.2. Using Pseudo Random Pattern Mode
6.16.1. Using PRBS Data Pattern Generator and Checker x
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs 6.16.1.2. Enabling the PRBS Data Generator in bonded designs 6.16.1.3. Enabling the PRBS Data Checker in non bonded design 6.16.1.4. Enabling the PRBS Checker in bonded designs 6.16.1.5. Disabling/Enabling PRBS Pattern Inversion
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs x
6.16.1.1.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in non bonded designs
6.16.1.2. Enabling the PRBS Data Generator in bonded designs x
6.16.1.2.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in bonded designs
6.16.1.3. Enabling the PRBS Data Checker in non bonded design x
6.16.1.3.1. Examples of Enabling the PRBS Data Checker
6.16.2. Using Pseudo Random Pattern Mode x
6.16.2.1. Enabling Pseudo Random Pattern Mode
7. Calibration x
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine 7.2. Calibration Registers 7.3. Power-up Calibration 7.4. User Recalibration 7.5. Calibration Example 7.6. Calibration Revision History
7.2. Calibration Registers x
7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers 7.2.2. Transceiver Channel Calibration Registers 7.2.3. Fractional PLL Calibration Registers 7.2.4. ATX PLL Calibration Registers 7.2.5. Capability Registers 7.2.6. Rate Switch Flag Register
7.4. User Recalibration x
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate Change
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate Change x
7.4.1.1. User Recalibration
7.5. Calibration Example x
7.5.1. ATX PLL Recalibration 7.5.2. Fractional PLL Recalibration 7.5.3. CDR/CMU PLL Recalibration 7.5.4. PMA Recalibration
8. Analog Parameter Settings x
8.1. Making Analog Parameter Settings using the Assignment Editor 8.2. Updating Quartus Settings File with the Known Assignment 8.3. Analog Parameter Settings List 8.4. Receiver General Analog Settings 8.5. Receiver Analog Equalization Settings 8.6. Transmitter General Analog Settings 8.7. Transmitter Pre-Emphasis Analog Settings 8.8. Transmitter VOD Settings 8.9. Dedicated Reference Clock Settings 8.10. Unused Transceiver RX Channels Settings 8.11. Analog Parameter Settings Revision History
8.4. Receiver General Analog Settings x
8.4.1. XCVR_A10_RX_LINK 8.4.2. XCVR_A10_RX_TERM_SEL 8.4.3. XCVR_VCCR_VCCT_VOLTAGE - RX
8.5. Receiver Analog Equalization Settings x
8.5.1. CTLE Settings 8.5.2. VGA Settings 8.5.3. Decision Feedback Equalizer (DFE) Settings
8.5.1. CTLE Settings x
8.5.1.1. XCVR_A10_RX_ONE_STAGE_ENABLE 8.5.1.2. XCVR_A10_RX_EQ_DC_GAIN_TRIM 8.5.1.3. XCVR_A10_RX_ADP_CTLE_ACGAIN_4S 8.5.1.4. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
8.5.2. VGA Settings x
8.5.2.1. XCVR_A10_RX_ADP_VGA_SEL
8.5.3. Decision Feedback Equalizer (DFE) Settings x
8.5.3.1. XCVR_A10_RX_ADP_DFE_FXTAP
8.6. Transmitter General Analog Settings x
8.6.1. XCVR_A10_TX_LINK 8.6.2. XCVR_A10_TX_TERM_SEL 8.6.3. XCVR_A10_TX_COMPENSATION_EN 8.6.4. XCVR_VCCR_VCCT_VOLTAGE - TX 8.6.5. XCVR_A10_TX_SLEW_RATE_CTRL
8.7. Transmitter Pre-Emphasis Analog Settings x
8.7.1. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T 8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T 8.7.3. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP 8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP 8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
8.8. Transmitter VOD Settings x
8.8.1. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
8.9. Dedicated Reference Clock Settings x
8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE 8.9.2. XCVR_A10_TX_XTX_PATH_ANALOG_MODE
9. Debugging Transceiver Toolkit x
9.1. Transceiver Toolkit GUI 9.2. Transceiver Debugging Flow Walkthrough 9.3. Linking Hardware Resource for Multiple FPGAs 9.4. Troubleshooting Common Errors 9.5. Debugging Transceiver Toolkit Revision History
9.1. Transceiver Toolkit GUI x
9.1.1. Main View Functions
9.2. Transceiver Debugging Flow Walkthrough x
9.2.1. Enabling Transceiver Toolkit Support 9.2.2. Programming Design into an Intel® FPGA 9.2.3. Loading Design to the Transceiver Toolkit 9.2.4. Creating Transceiver Links 9.2.5. Running Link Test
9.2.4. Creating Transceiver Links x
9.2.4.1. Transceiver Toolkit Parameter Settings 9.2.4.2. Verifying Hardware Connections
9.2.5. Running Link Test x
9.2.5.1. Running BER Tests 9.2.5.2. Link Optimization Tests
9.3. Linking Hardware Resource for Multiple FPGAs x
9.3.1. Linking One Design to One Device 9.3.2. Linking Two Designs to Two Devices 9.3.3. Linking One Design on Two Devices 9.3.4. Linking Designs and Devices on Separate Boards
1. Arria® 10 Transceiver PHY Overview
2. Implementing Protocols in Arria 10 Transceivers
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Arria 10 Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Analog Parameter Settings
9. Debugging Transceiver Toolkit

2.6.4.7.1. 1G/10GbE Register Definitions

The Avalon® memory-mapped interface master signals provide access to the control and status registers.

The following table specifies the control and status registers that you can access over the Avalon® memory-mapped interface. A single address space provides access to all registers.

Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Do not write to any register that is not specified.
Table 144.  1G/10GbE Register Definitions
Word Addr Bit R/W Name Description
0x4B0 0 RW Reset SEQ When set to 1, resets the 10GBASE-KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart Auto-Negotiation (AN), Link Training (LT), or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
1 RW Disable AN Timer AN disable timer. If disabled ( Disable AN Timer = 1) , AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature. In addition, software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state. To enable this timer set Disable AN Timer = 0.
2 RW Disable LF Timer When set to 1, disables the Link Fail timer. When set to 0, the Link Fault timer is enabled.
3 RW fail_lt_if_ber When set to 1, the last LT measurement is a non-zero number. Treat this as a failed run. 0 = Normal.
7:4 RW SEQ Force Mode[2:0]

Other than the "No force" mode (0x4B0[7:4] = 4'b0000), you must write the Reset SEQ (0x4B0[0]) to 1 when switching to the required data mode by changing (forcing) the 0x4B0[7:4] bits. The following encodings are defined:

  • 0000: No force
  • 0001: GbE
  • 0010: XAUI
  • 0100: 10GBASE-R
  • 0101: 10GBASE-KR
  • 1100: 10GBASE-KR FEC
8 RW Enable Arria 10 Calibration When set to 1, it enables the Arria 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured.
16 RW KR FEC enable 171.0 When set to 1, FEC is enabled. When set to 0, FEC is disabled. Resets to the CAPABLE_FEC parameter value.
17 RW KR FEC enable err ind 171.1 When set to 1, KR PHY FEC decoding errors are signaled to the PCS. When set to 0, FEC errors are not signaled to the PCS. See Clause 74.8.3 of IEEE 802.3ap-2007 for details.
18 RW KR FEC request When set to 1, enables the FEC request. When this bit changes, you must assert the Reset SEQ bit (0x4B0[0]) to renegotiate with the new value. When set to 0, disables the FEC request.
0x4B1 0 R SEQ Link Ready When asserted, the sequencer indicates the link is ready.
1 R SEQ AN timeout When asserted, the sequencer has had an AN timeout. This bit is latched and is reset when the sequencer restarts AN.
2 R SEQ LT timeout When set, indicates that the sequencer has had a timeout.
13:8 R SEQ Reconfig Mode[5:0] Specifies the sequencer mode for PCS reconfiguration. The following modes are defined:
  • Bit 8, mode[0]: AN mode
  • Bit 9, mode[1]: LT Mode
  • Bit 10, mode[2]: 10G data mode
  • Bit 11, mode[3]: GbE data mode
  • Bit 12, mode[4]: Reserved for XAUI
  • Bit13, mode[5]: 10G FEC mode
16 R KR FEC ability 170.0 When set to 1, indicates that the 10GBASE-KR PHY supports FEC. Set as parameter SYNTH_FEC. For more information, refer to Clause 45.2.1.84 of IEEE 802.3ap-2007.
17 R KR FEC err ind ability 170.0 When set to 1, indicates that the 10GBASE-KR PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
0x4B2 0:10 RW Reserved —
11 RWSC KR FEC TX Error Insert Writing a 1 inserts one error pulse into the TX FEC depending on the transcoder and burst error settings.
31:15 RWSC Reserved —
0x4B5 to 0x4BF     Reserved for 40G KR Intentionally left empty for address compatibility with 40G MAC + PHY KR solutions.
0x4C0 36 0 RW AN enable When set to 1, enables the AN function. The default value is 1. For additional information, refer to bit 7.0.12 in Clause 73.8 Management Register Requirements of IEEE 802.3ap-2007.
1 RW AN base pages ctrl When set to 1, the user base pages are enabled. You can send any arbitrary data via the user base page low/high bits. When set to 0, the user base pages are disabled and the state machine generates the base pages to send.
2 RW AN next pages ctrl When set to 1, the user next pages are enabled. You can send any arbitrary data via the user next page low/high bits. When set to 0, the user next pages are disabled. The state machine generates the null message to send as next pages.
3 RW Local device remote fault When set to 1, the local device signals Remote Faults in the AN pages. When set to 0, a fault has not occurred.
4 RW Force TX nonce value When set to 1, forces the TX nonce value to support some UNH testing modes. When set to 0, this is normal operation.
5 RW Override AN Parameters Enable When set to 1, overrides the AN_TECH, AN_FEC, and AN_PAUSE parameters and uses the bits in 0x4C3 instead. You must reset the Sequencer to reconfigure and restart into AN mode. When set to 0, this is normal operation and is used with 0x4B0 bit 0 and 0x4C3 bits[30:16].
0x4C1 0 RW Reset AN When set to 1, resets all the 10GBASE-KR AN state machines. This bit is self clearing.
4 RW Restart AN TX SM When set to 1, restarts the 10GBASE-KR TX state machine. This bit self clears and is active only when the TX state machine is in the AN state. For more information, refer to bit 7.0.9 in Clause 73.8 Management Register Requirements of IEEE 802.3ap-2007.
8 RW AN Next Page When asserted, new next page (NP) info is ready to send. The data is in the XNP TX registers. When 0, the TX interface sends null pages. This bit self clears. NP is encoded in bit D15 of Link Codeword. For more information, refer to Clause 73.6.9 and bit 7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap-2007.
0x4C2 1 RO AN page received When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE 802.3ap-2007.
2 RO AN Complete When asserted, AN has completed. When 0, AN is in progress. For more information, refer to bit 7.1.5 in Clause 73.8 of IEEE 802.3ap-2007.
3 RO AN ADV Remote Fault When set to 1, fault information has been sent to the link partner. When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. For more information, refer to Clause 73.6.7 of and bit 7.16.13 of IEEE 802.3ap‑2007.
4 RO AN RX SM Idle When set to 1, the AN state machine is in the idle state. Incoming data is not Clause 73 compatible. When 0, the AN is in progress.
5 RO AN Ability When set to 1, the transceiver PHY is able to perform AN. When set to 0, the transceiver PHY is not able to perform AN. If your variant includes AN, this bit is tied to 1. For more information, refer to bits 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
6 RO AN Status When set to 1, link is up. When 0, the link is down. The current value clears when the register is read. For more information, refer to bit 7.1.2 of Clause 45 of IEEE 802.3ap-2007.
7 RO LP AN Ability When set to 1, the link partner is able to perform AN. When 0, the link partner is not able to perform AN. For more information, refer to bit 7.1.0 of Clause 45 of IEEE 802.3ap-2007.
8 RO FEC negotiated – enable FEC from SEQ When set to 1, the PHY is negotiated to perform FEC. When set to 0, the PHY is not negotiated to perform FEC.
0x4C2 9 RO Seq AN Failure When set to 1, a sequencer AN failure has been detected. When set to 0, an AN failure has not been detected.
17:12 RO KR AN Link Ready[5:0] Provides a one-hot encoding of an_receive_idle = true and link status for the supported link as described in Clause 73.10.1. The following encodings are defined:
  • 6'b000000: 1000BASE-KX
  • 6'b000001: 10GBASE-KX4
  • 6'b000100: 10GBASE-KR
  • 6'b001000: 40GBASE-KR4
  • 6'b010000: 40GBASE-CR4
  • 6'b100000: 100GBASE-CR10
0x4C3 15:0 RW User base page low The AN TX state machine uses these bits if the AN base pages ctrl bit is set. The following bits are defined:
  • [15]: Next page bit
  • [14]: ACK, controlled by the SM
  • [13]: Remote Fault bit
  • [12:10]: Pause bits
  • [9:5]: Echoed nonce, set by the state machine
  • [4:0]: Selector
The auto generation TX state machine generates the PRBS bit 49.
21:16 RW Override AN_TECH[5:0]

AN_TECH value to override. The following bits are defined:

  • Bit-16 = AN_TECH[0]= 1000BASE-KX
  • Bit-18 = AN_TECH[2] = 10GBASE-KR
You must set 0xC0 bit-5 for this to take effect .
25:24 RW Override AN_FEC[1:0] AN_FEC value to override. The following bits are defined:
  • Bit-24 = AN_FEC [0] = Capability
  • Bit-25 = AN_FEC [1] = Request
You must set 0xC0 bit-5 for this to take effect.
30:28 RW Override AN_PAUSE[2:0] AN_PAUSE value to override. The following bits are defined:
  • Bit-28 = AN_PAUSE [0] = Pause Ability
  • Bit-29 = AN_PAUSE [1] = Asymmetric Direction
  • Bit-30 = AN_PAUSE [2] = Reserved
You must set 0xC0 bit-5 for this to take effect.
0x4C4 31:0 RW User base page high The AN TX state machine uses these bits if the AN base pages ctrl bit is set. The following bits are defined:
  • [29:5]: Correspond to page bits 45:21, the technology ability.
  • [4:0]: Correspond to bits 20:16, the TX nonce bits.
The AN TX state machine generates the PRBS bit 49.
0x4C5 15:0 RW User Next page low The AN TX state machine uses these bits if the AN next pages ctrl bit is set. The following bits are defined:
  • [15]: Next page bit
  • [14]: ACK, controlled by the state machine
  • [13]: Message Page (MP) bit
  • [12]: ACK2 bit
  • [11]: Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is generated by the AN TX state machine.
0x4C6 31:0 RW User Next page high The AN TX state machine uses these bits if the AN next pages ctrl bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the PRBS bit, is generated by the AN TX state machine.
0x4C7 15:0 RO LP base page low The AN RX state machine receives these bits from the link partner. The following bits are defined:
  • [15] Next page bit
  • [14] ACK, which is controlled by the state machine
  • [13] RF bit
  • [12:10] Pause bits
  • [9:5] Echoed nonce which are set by the state machine
  • [4:0] Selector
0x4C8 31:0 RO LP base page high The AN RX state machine received these bits from the link partner. The following bits are defined:
  • [31:30]: Reserved
  • [29:5]: Correspond to page bits [45:21], the technology ability
  • [4:0]: Correspond to bits [20:16], the TX Nonce bits
0x4C9 15:0 RO LP Next page low The AN RX state machine receives these bits from the link partner. The following bits are defined:
  • [15]: Next page bit
  • [14]: ACK which is controlled by the state machine
  • [13]: MP bit
  • [12] ACK2 bit
  • [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
0x4CA 31:0 RO LP Next page high The AN RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16].
0x4CB 24:0 RO AN LP ADV Tech_A[24:0] Received technology ability field bits of Clause 73 Auto-Negotiation. The 10GBASE‑KR PHY supports A0 and A2. The following protocols are defined:
  • A0 1000BASE-KX
  • A1 10GBASE-KX4
  • A2 10GBASE-KR
  • A3 40GBASE-KR4
  • A4 40GBASE-CR4
  • A5 100GBASE-CR10
  • A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
26:25 RO AN LP ADV FEC_F[1:0] Received FEC ability bits (F0:F1) is encoded in bits D46:D47 of the base Link Codeword. F0 is FEC ability. F1 is FEC requested. See Clause 73.6.5 of IEEE 802.3ap-2007 for details.
27 RO AN LP ADV Remote Fault Received Remote Fault (RF) ability bits. RF is encoded in bit D13 of the base link codeword in Clause 73 AN. For more information, refer to Clause 73.6.7 and bits AN LP base page ability register AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap‑2007.
30:28 RO AN LP ADV Pause Ability_C[2:0] Received pause ability bits. Pause (C0:C1) is encoded in bits D11:D10 of the base link codeword in Clause 73 AN as follows:
  • C0 is the same as PAUSE as defined in Annex 28B
  • C1 is the same as ASM_DIR as defined in Annex 28B
  • C2 is reserved
For more information, refer to bits AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap‑2007.
0x4D0 0 RW Link Training enable When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR start-up protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.1) of IEEE 802.3ap‑2007.
1 RW dis_max_wait_tmr When set to 1, disables the LT max_wait_timer . Used for characterization mode when setting much longer bit error rate (BER) timer values.
2 RW quick_mode When set to 1, only the init and preset values calculate the best BER.
3 RW pass_one When set to 1, the BER algorithm considers more than the first local minimum when searching for the lowest BER. The default value is 1.
7:4 RW main_step_cnt [3:0] Specifies the number of equalization steps for each main tap update. There are about 20 settings for the internal algorithm to test. The valid range is 1-15. The default value is 4'b0010.
11:8 RW prpo_step_cnt [3:0] Specifies the number of equalization steps for each pre- and post-tap update. From 16-31 steps are possible. The default value is 4'b0001.
0x4D0 14:12 RW equal_cnt [2:0]

Adds hysteresis to the error count to avoid local minimums. The following values are defined:

  • 000 = 0
  • 001 = 1
  • 010 = 2
  • 011 = 3
  • 100 = 4
  • 101 = 8
  • 110 = 16
  • 111 = Reserved
The default value is 010.
15 RW disable Initialize PMA on max_wait_timeout When set to 1, PMA values (VOD, pre-tap, post-tap) are not initialized upon entry into the Training_Failure state. This happens when max_wait_timer_done, which sets training_failure = true (reg 0x4D2 bit 3). Used for University of New Hampshire (UNH) testing. When set to 0, PMA values are initialized upon entry into Training_Failure state. Refer to Figure 72-5 of IEEE 802.3ap-2007 for more details.
16 RW Ovride LP Coef enable When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link Training logic to determine the link partner coefficients. Used with 0x4D1 bit-4 and 0x4D4 bits[7:0].
17 RW Ovride Local RX Coef enable When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0x4D1 bit-8 and 0x4D4 bits[23:16]. The default value is 1.
0x4D0 22 RW adp_ctle_mode Reserved. Default = 000
28:24 RW Manual ctle Reserved
31:29 RW max_post_step[2:0] Reserved
0x4D1 0 RW Restart Link training When set to 1, resets the 10GBASE-KR start-up protocol. When set to 0, continues normal operation. This bit self clears. For more information, refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.0) IEEE 802.3ap‑2007.
4 RW Updated TX Coef new When set to 1, there are new link partner coefficients available to send. The LT logic starts sending the new values set in 0x4D4 bits[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears. Must enable this override in 0x4D0 bit 16.
8 RW Updated RX coef new When set to 1, new local device coefficients are available. The LT logic changes the local TX equalizer coefficients as specified in 0x4D4 bits[23:16]. When set to 0, continues normal operation. This bit self clears. Must enable the override in 0x4D0 bit17.
0x4D2 0 RO Link Trained - Receiver status When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress. For more information, refer to the state variable rx_trained as defined in Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control register bit 10GBASE_KR PMD status register bit (1.151.0) of IEEE 802.3ap‑2007.
1 RO Link Training Frame lock When set to 1, the training frame delineation has been detected. When set to 0, the training frame delineation has not been detected. For more information, refer to the state variable frame_lock as defined in Clause 72.6.10.3.1 and 10GBASE_KR PMD status register bit 10GBASE_KR PMD status register bit (1.151.1) of IEEE 802.3ap‑2007.
2 RO Link Training Start-up protocol status When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state training as defined in Clause 72.6.10.3.1 and 10GBASE_KR PMD status register bit (1.151.2) of IEEE 802.3ap‑2007.
3 RO Link Training failure When set to 1, a training failure has been detected. When set to 0, a training failure has not been detected. For more information, refer to the state variable training_failure as defined in Clause 72.6.10.3.1 and bit 10GBASE_KR PMD status register bit (1.151.3) of IEEE 802.3ap‑2007.
4 RO Link Training Error When set to 1, excessive errors occurred during Link Training. When set to 0, the BER is acceptable.
5 RO Link Training Frame lock Error When set to 1, indicates a frame lock was lost during Link Training. If the tap settings specified by the fields of 0x4D5 are the same as the initial parameter value, the frame lock error was unrecoverable.
6 RO RXEQ Frame Lock Loss Frame lock not detected at some point during RXEQ, possibly triggering conditional RXEQ mode.
7 RO CTLE Fine-grained Tuning Error Could not determine the best CTLE due to maximum BER limit at each step in the fine-grained tuning mode.
0x4D3 9:0 RW ber_time_frames Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_frames is 0. The following values are defined:
  • A value of 2 is about 103 bytes
  • A value of 20 is about 104 bytes
  • A value of 200 is about 105 bytes
The default value for simulation is 2'b11. The default value for hardware is 0.
19:10 RW ber_time_k_frames Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames = 0 for time/bits to match the following values:
  • A value of 3 is about 107 bits = About 1.3 ms
  • A value of 25 is about 108 bits = About 11 ms
  • A value of 250 is about 109 bits = About 110 ms
The default value for simulation is 0. The default value for hardware is 0x415.
29:20 RW ber_time_m_frames Specifies the number of millions of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_k_frames = 4'd1000 = 0x43E8 for time/bits to match the following values:
  • A value of 3 is about 1010 bits = About 1.3 seconds
  • A value of 25 is about 10 11 bits = About 11 seconds
  • A value of 250 is about 1012 bits = About 110 seconds
0x4D4 5:0 RO or RW LD coefficient update[5:0] Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride Coef enable control bit, these bits become writable. The following fields are defined:
  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to bit 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE 802.3ap-2007.
6 RO or RW LD Initialize Coefficients When set to 1, requests the link partner coefficients be set to configure the TX equalizer to its INITIALIZE state. When set to 0, continues normal operation. For more information, refer to 10G BASE-KR LD coefficient update register bits (1.154.12) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
7 RO or RW LD Preset Coefficients When set to 1, requests the link partner coefficients be set to a state where equalization is turned off. When set to 0 the link operates normally. For more information, refer to bit 10GBASE-KR LD coefficient update register bit (1.154.13) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
13:8 RO LD coefficient status[5:0] Status report register for the contents of the second, 16-bit word of the training frame most recently sent from the local device control channel. The following fields are defined:
  • [5:4]: Coefficient (post-tap)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LD status report register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE 802.3ap-2007.
0x4D4 14 RO Link Training ready - LD Receiver ready When set to 1, the local device receiver has determined that training is complete and it is prepared to receive data. When set to 0, the local device receiver requests that training continue. Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to bit 10GBASE-KR LD status report register bit (1.155.15) in Clause 45.2.1.81 of IEEE 802.3ap-2007.
21:16 RO or RW LP coefficient update[5:0] Reflects the contents of the first 16-bit word of the training frame most recently received from the control channel.

Normally the bits in this register are read only; however, when training is disabled by setting low the KR training enable control bit, these bits become writable. The following fields are defined:

  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])

For more information, refer to bit 10GBASE-KR LP coefficient update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.

22 RO or RW LP Initialize Coefficients When set to 1, the local device transmit equalizer coefficients are set to the INITIALIZE state. When set to 0, normal operation continues. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to bit 10GBASE-KR LP coefficient update register bits (1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
0x4D4 23 RO or RW LP Preset Coefficients When set to 1, the local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The function and values of the preset bit are defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to bit 10GBASE-KR LP coefficient update register bits (1.152.13) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
29:24 RO LP coefficient status[5:0] Status report register reflecting the contents of the second, 16-bit word of the training frame most recently received from the control channel. The following fields are defined:
  • [5:4]: Coefficient (+1)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LP status report register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE 802.3ap-2007.
30 RO LP Receiver ready When set to 1, the link partner receiver has determined that training is complete and is prepared to receive data. When set to 0, the link partner receiver is requesting that training continue.

Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to bit 10GBASE-KR LP status report register bits (1.153.15) in Clause 45.2.1.79 of IEEE 802.3ap-2007.

0x4D5 4:0 R LT VOD setting Stores the most recent VOD setting that LT specified. It reflects Link Partner commands to fine‑tune the VOD.
13:8 R LT Post-tap setting Stores the most recent post‑tap setting that LT specified. It reflects Link Partner commands to fine‑tune the TX pre‑emphasis taps.
20:16 R LT Pre-tap setting Stores the most recent pre-tap setting that LT specified. It reflects Link Partner commands to fine‑tune the TX pre‑emphasis taps.
0x4D5 27:24 R RXEQ CTLE Setting Most recent ctle_rc setting sent to the reconfig bundle during RX equalization.
29:28 R RXEQ CTLE Mode Most recent ctle_mode setting sent to the reconfig bundle during RX equalization.
31:30 R RXEQ DFE Mode Most recent dfe_mode setting sent to the reconfig bundle during RX equalization.
0x4D6 4:0 RW LT VODMAX ovrd Override value for the VMAXRULE parameter. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only effects the local device TX output for the channel specified.

This value must be greater than the INITMAINVAL parameter for proper operation. Note this also overrides the PREMAINVAL parameter value.

5 RW LT VODMAX ovrd Enable When set to 1, enables the override value for the VMAXRULE parameter stored in the LT VODMAX ovrd register field.
12:8 RW LT VODMin ovrd Override value for the VODMINRULE parameter. When enabled, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be less than the INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation.

13 RW LT VODMin ovrd Enable When set to 1, enables the override value for the VODMINRULE parameter stored in the LT VODMin ovrd register field.
21:16 RW LT VPOST ovrd Override value for the VPOSTRULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation.

22 RW LT VPOST ovrd Enable When set to 1, enables the override value for the VPOSTRULE parameter stored in the LT VPOST ovrd register field.
28:24 RW LT VPre ovrd Override value for the VPRERULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value greater than the INITPREVAL parameter for proper operation.

29 RW LT VPre ovrd Enable When set to 1, enables the override value for the VPRERULE parameter stored in the LT VPre ovrd register field.
0x4D7 to 0x4FF     Reserved for 40G KR Left empty for address compatibility with 40G MAC+PHY KR solution.
Related Information
36 These register bits are only applicable to the 10GBASE-KR mode.
Level Two Title