Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents
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2.6.4.7.1. 1G/10GbE Register Definitions

The Avalon® memory-mapped interface master signals provide access to the control and status registers.

The following table specifies the control and status registers that you can access over the Avalon® memory-mapped interface. A single address space provides access to all registers.

Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Do not write to any register that is not specified.
Table 144.  1G/10GbE Register Definitions
Word Addr Bit R/W Name