Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

5.2.1.1.1. Phase Compensation Mode

In Phase Compensation mode, the TX Core FIFO decouples phase variations between tx_coreclkin and PCS_clkout_x2(tx). In this mode, read and write of the TX Core FIFO can be driven by clocks from asynchronous clock sources but must be same frequency. You can use tx_coreclkin (FPGA fabric clock) or tx_clkout1 (TX parallel clock) to clock the write side of the TX Core FIFO.

Note: Phase Compensation mode, TX parallel data is valid for every low speed clock cycle, and tx_enh_data_valid signal should be tied with