In Phase Compensation mode, the TX Core FIFO decouples phase variations between tx_coreclkin and PCS_clkout_x2(tx). In this mode, read and write of the TX Core FIFO can be driven by clocks from asynchronous clock sources but must be same frequency. You can use tx_coreclkin (FPGA fabric clock) or tx_clkout1 (TX parallel clock) to clock the write side of the TX Core FIFO.
Note: Phase Compensation mode, TX parallel data is valid for every low speed clock cycle, and tx_enh_data_valid signal should be tied with 1'b1.
Note: Phase Compensation can also be used in double rate transfer mode, where the FPGA fabric data width is doubled to allow the FPGA fabric clock to run at half rate. The double rate transfer mode is set in the Native PHY IP Parameter Editor. Refer to the "Transmitter Data Path Interface Clocking" and "Receiver Data Path Interface Clocking" sections in the PLLs and Clock Networks chapter for details about the clock frequencies, when using FIFO single and double rate transfer mode.