Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes

Table 261.  Word Aligner Pattern Length for Various Word Aligner Modes
PCS-PMA Interface Width Supported Word Aligner Modes Supported Word Aligner Pattern Lengths rx_std_wa_patternalign behavior rx_syncstatus behavior rx_patterndetect behavior
8 Bit slip 8 rx_std_wa_patternalign has no effect on word alignment. The single width word aligner updates the word boundary, only when the FPGA fabric-asserted BITSLIP signal toggles. N/A N/A
Manual 8, 16 Word alignment is controlled by rx_std_wa_patternalign and is edge-sensitive to this signal. Asserted high for one parallel clock cycle when the word aligner aligns to a new boundary. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
10 Bit slip 7 rx_std_wa_patternalign has no effect on word alignment. The single width word aligner updates the word boundary, only when the FPGA fabric-asserted BITSLIP signal toggles. N/A N/A
Manual 7, 10 Word alignment is controlled by rx_std_wa_patternalign and is level-sensitive to this signal. Asserted high for one parallel clock cycle when the word aligner aligns to a new boundary. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
Deterministic latency (CPRI mode only) 10 Word alignment is controlled by rx_std_wa_patternalign (edge-sensitive to this signal) and the state machine works in conjunction with PMA to achieve deterministic latency on the RX path for CPRI and OBSAI applications.
Synchronous State Machine 7, 10 rx_std_wa_patternalign has no effect on word alignment. Stays high as long as the synchronization conditions are satisfied. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
16 Bit slip 16 rx_std_wa_patternalign has no effect on word alignment. The double width word aligner updates the word boundary, only when the FPGA fabric-asserted BITSLIP signal toggles. N/A N/A
Manual 8, 16, 32 Word alignment is controlled by rising-edge of rx_std_wa_patternalign. Stays high after the word aligner aligns to the word alignment pattern. Goes low on receiving a rising edge on rx_std_wa_patternalign until a new word alignment pattern is received. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
20 Bit slip 7 rx_std_wa_patternalign has no effect on word alignment. The double width word aligner updates the word boundary, only when the FPGA fabric-asserted BITSLIP signal toggles. N/A N/A
Manual 7, 10, 20, 40 Word alignment is controlled by rising edge of rx_std_wa_patternalign. Stays high after the word aligner aligns to the word alignment pattern. Goes low on receiving a rising edge on rx_std_wa_patternalign until a new word alignment pattern is received. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
Deterministic latency (CPRI mode only) 10 Word alignment is controlled by rx_std_wa_patternalign (edge-sensitive to this signal) and the deterministic latency state machine which controls the PMA to achieve deterministic latency on the RX path for CPRI and OBSAI applications.
Synchronous State Machine 7, 10, 20 FPGA fabric-driven rx_std_wa_patternalign signal has no effect on word alignment. Stays high as long as the synchronization conditions are satisfied. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.

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