Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Public
Document Table of Contents

5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes

Table 261.  Word Aligner Pattern Length for Various Word Aligner Modes
PCS-PMA Interface Width Supported Word Aligner Modes Supported Word Aligner Pattern Lengths rx_std_wa_patternalign behavior rx_syncstatus behavior rx_patterndetect behavior
8 Bit slip 8 rx_std_wa_patternalign has no effect on word alignment. The single width word aligner updates the word boundary, only when the FPGA fabric-asserted BITSLIP signal toggles. N/A N/A
Manual 8, 16 Word alignment is controlled by rx_std_wa_patternalign and is edge-sensitive to this signal. Asserted high for one parallel clock cycle when the word aligner aligns to a new boundary. Asserted high for one parallel clock cycle when the word alignment pattern appears in the current word boundary.
10 Bit slip 7