Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.6.5.3.2. Timing Constraints

Constrain the PHY based on the fastest speed. For example, if you configure the PHY as 1G/2.5G, constrain it based on 2.5G.

Table 155.  Timing Constraints
PHY Configuration Constrain PHY for
2.5G 2.5G datapath
1G/2.5G 2.5G datapath
1G/2.5G/10G (MGBASE-T) 10G and 1G/2.5G datapath
10M/100M/1G/2.5G/5G/10G (USXGMII) 10G datapath
When you select MGBASE-T configuration for external PHY with 1G/2.5G/10G operating mode, Intel® recommends that you add the following constraints in the timing constraint file to constrain the PHY for the 10G datapath as well as the 1G/2.5G datapath:
Note: Prior to editing the timing constraint file, you must define the PHY hierarchy path to <Installation Directory>/ip/altera/ethernet/alt_mge_phy/example/alt_mge_phy_multi_speed_10g.sdc.
  • Create generated clocks for 1G/2.5G datapath. Since the 1G and 2.5G hard PCS configurations are the same, the constraint is set based on 2.5G datapath. For example:
    # Create the 1G/2.5G RX clock
    set rx_pma_clk_1g2p5g_name  "${ch_phy}rx_pma_clk_1g2p5g"
    set clock_node              "${ch_phy}$native_ls_inst$rx_pma_clk_1g2p5g_target"
    create_generated_clock -name $rx_pma_clk_1g2p5g_name -source [get_clock_info -targets refclk_1g2p5g] -divide_by 2 -multiply_by 5 [get_pins $clock_node] -add
        
    set rx_clk_1g2p5g_name      "${ch_phy}rx_clk_1g2p5g"
    set clock_source            "${ch_phy}$native_ls_inst$rx_pcs_clk_1g2p5g_source"
    set clock_node              "${ch_phy}$native_ls_inst$rx_pcs_clk_1g2p5g_target"
    create_generated_clock -name $rx_clk_1g2p5g_name -source [get_pins $clock_source] -master_clock $rx_pma_clk_1g2p5g_name -divide_by 2 -multiply_by 1 [get_pins $clock_node] -add
        
    set rx_clkout_1g2p5g_name   "${ch_phy}rx_clkout_1g2p5g"
    set clock_source            "${ch_phy}$native_ls_inst$rx_pld_clk_1g2p5g_source"
    set clock_node              "${ch_phy}$native_ls_inst$rx_pld_clk_10g_target"
    create_generated_clock -name $rx_clkout_1g2p5g_name -source [get_pins $clock_source] -master_clock $rx_pma_clk_1g2p5g_name -divide_by 2 -multiply_by 1 [get_pins $clock_node] -add
        
    # Create the 1G/2.5G TX clock
    set tx_pma_clk_1g2p5g_name  "${ch_phy}tx_pma_clk_1g2p5g"
    set clock_node              "${ch_phy}$native_ls_inst$tx_pma_clk_1g2p5g_target"
    create_generated_clock -name $tx_pma_clk_1g2p5g_name -source [get_clock_info -targets $serclk_1g2p5g] -divide_by 5 -multiply_by 1 [get_pins $clock_node] -add
        
    set tx_clk_1g2p5g_name      "${ch_phy}tx_clk_1g2p5g"
    set clock_source            "${ch_phy}$native_ls_inst$tx_pcs_clk_1g2p5g_source"
    set clock_node              "${ch_phy}$native_ls_inst$tx_pcs_clk_1g2p5g_target"
    create_generated_clock -name $tx_clk_1g2p5g_name -source [get_pins $clock_source] -master_clock $tx_pma_clk_1g2p5g_name -divide_by 2 -multiply_by 1 [get_pins $clock_node] -add
        
    set tx_clkout_1g2p5g_name   "${ch_phy}tx_clkout_1g2p5g"
    set clock_source            "${ch_phy}$native_ls_inst$tx_pld_clk_1g2p5g_source"
    set clock_node              "${ch_phy}$native_ls_inst$tx_pld_clk_10g_target"
    create_generated_clock -name $tx_clkout_1g2p5g_name -source [get_pins $clock_source] -master_clock $tx_pma_clk_1g2p5g_name -divide_by 2 -multiply_by 1 [get_pins $clock_node] -add 
    
    Note: The clock node for rx_clkout_1g2p5g_name and tx_clkout_1g2p5g_name is set to rx_pld_clk_10g_target and tx_pld_clk_10g_target respectively because the design for this configuration is compiled with respect to the fastest speed, which is 10G. As such, this node connection that has been created by Intel® Quartus® Prime software is reused to set the timing constraint for 1G/2.5G datapath.
  • Create default clock for 10G datapath. The Timing Analyzer does not create these clocks due to the creation of 1G/2.5G clocks in the above constraint. Also, the Timing Analyzer does not create clocks that come from the same master clock.
    # Create the 10G (default) clocks which were not created by the IPSTA due to 1G/2.5G clocks just created above
    set rx_clkout_10g_name  "${ch_phy}rx_clkout"
    set master_src          "${ch_phy}rx_pma_clk"
    set clock_source        "${ch_phy}$native_ls_inst$rx_pld_clk_10g_source"
    set clock_node          "${ch_phy}$native_ls_inst$rx_pld_clk_10g_target"
    create_generated_clock -name $rx_clkout_10g_name -source [get_pins $clock_source] -master_clock $master_src [get_pins $clock_node] -add
        
    set tx_clkout_10g_name  "${ch_phy}tx_clkout"
    set master_src          "${ch_phy}tx_pma_clk"
    set clock_source        "${ch_phy}$native_ls_inst$tx_pld_clk_10g_source"
    set clock_node          "${ch_phy}$native_ls_inst$tx_pld_clk_10g_target"
    create_generated_clock -name $tx_clkout_10g_name -source [get_pins $clock_source] -master_clock $master_src [get_pins $clock_node] -add
    
    # PMA clock name for setting false path
        set rx_pma_clk_10g_name  "${ch_phy}rx_pma_clk"
        set tx_pma_clk_10g_name  "${ch_phy}tx_pma_clk"
    
    where 1g2p5g and 10g are referred to the 1G/2.5G and 10G clocks respectively.
  • Set false path from 10G clock to 1G/2.5G PHY logic and vice versa. Since the 1G/2.5G PHY logic is not running at 10G clock speed, you do not have to ensure timing closure for 1G/2.5G datapath at 10G clock. For example:
    set_false_path -from [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"] -to [get_registers "*|alt_mge16_pcs_pma:*|* $hssi_8g_pcs_if"]
    set_false_path -from [get_registers "*|alt_mge16_pcs_pma:*|* $hssi_8g_pcs_if"] -to [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"]
    
    where the path indicated by 10g is associated to the 10G clock, whereas the alt_mge16_pcs_pma path indicates the 1G/2.5G PHY logic.
  • Since the 10G PHY logic is not running at 1G/2.5G clock, you do not need to ensure timing closure for 10G datapath at the slower clock speed. False path is set from 1G/2.5G clock to 10G PHY logic and vice versa. For example:
    set_false_path -from [get_clocks "$rx_pma_clk_1g2p5g_name $rx_clk_1g2p5g_name $rx_clkout_1g2p5g_name $tx_pma_clk_1g2p5g_name $tx_clk_1g2p5g_name $tx_clkout_1g2p5g_name"] -to [get_registers "*|alt_mge_phy_xgmii_pcs:*|* $hssi_10g_pcs_if"]
    set_false_path -from [get_registers "*|alt_mge_phy_xgmii_pcs:*|* $hssi_10g_pcs_if"] -to [get_clocks "$rx_pma_clk_1g2p5g_name $rx_clk_1g2p5g_name $rx_clkout_1g2p5g_name $tx_pma_clk_1g2p5g_name $tx_clk_1g2p5g_name $tx_clkout_1g2p5g_name"]
    
    where the path indicated by 1g2p5g are associated to the 1G/2.5G clocks, whereas the alt_mge_phy_xgmii_pcs indicates the 10G PHY logic.

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