Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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5.1.6.2. Lock-to-Data Mode

During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data at the receiver input. Depending on the phase difference between the incoming data and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO.

Note: The PFD is inactive in LTD mode. The rx_is_lockedtoref status signal toggles randomly and is not significant in LTD mode.

After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. The actual lock time depends on the transition density of the incoming data and the parts per million (ppm) difference between the receiver input reference clock and the upstream transmitter reference clock. The rx_is_lockedtodata signal toggles until the CDR sees valid data; therefore, you should hold receiver PCS logic in reset (rx_digitalreset) for a minimum of 4 µs after rx_is_lockedtodata remains continuously asserted.

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