Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

7.2.5. Capability Registers

Capability registers allow you to read calibration status through the Avalon® memory-mapped interface reconfiguration. They are soft logic and reside in the FPGA fabric.

Reading capability registers does not require bus arbitration. You can read them during the calibration process.

To use capability registers to check calibration status, you must enable the capability registers when generating the Native PHY or PLL IP cores. To enable the capability registers, select the Enable capability registers option in the Dynamic Reconfiguration tab.

The tx_cal_busy and rx_cal_busy signals from the hard PHY are from the same hardware and change state (high/low) concurrently during calibration. The register bits 0x281[5:4] are defined to solve this issue. This prevents a TX channel being affected by RX calibration, or an RX channel being affected by TX calibration. This feature cannot be enabled, when a Simplex TX and Simplex RX channel merging is involved. To merge a Simplex TX and a Simplex RX channel into one physical channel, refer to Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks.

Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals

Figure 283. An Example of an AND Gate used as Customized LogicThe customized gates shown in the following figure are an example and not a unique solution
The capability register is not available for merging a Simplex TX and a Simplex RX signal into the same physical channel. The tx_cal_busy_out and rx_cal_busy_out signals share the same port. So, you should build customized gating logic to separate them.
  • The tx_cal_busy_out_en signal enables the tx_cal_busy output.
  • The rx_cal_busy_out_en signal enables the rx_cal_busy output.