Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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7.2.5. Capability Registers

Capability registers allow you to read calibration status through the Avalon® memory-mapped interface reconfiguration. They are soft logic and reside in the FPGA fabric.

Reading capability registers does not require bus arbitration. You can read them during the calibration process.

To use capability registers to check calibration status, you must enable the capability registers when generating the Native PHY or PLL IP cores. To enable the capability registers, select the Enable capability registers option in the Dynamic Reconfiguration tab.

The tx_cal_busy and rx_cal_busy signals from the hard PHY are from the same hardware and change state (high/low) concurrently during calibration. The register bits 0x281[5:4] are defined to solve this issue. This prevents a TX channel being affected by RX calibration, or an RX channel being affected by TX calibration. This feature cannot be enabled, when a Simplex TX and Simplex RX channel merging is involved. To merge a Simplex TX and a Simplex RX channel into one physical channel, refer to Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks.

Rules to Build Customized Gating Logic to Separate tx_cal_busy and rx_cal_busy signals

Figure 283. An Example of an AND Gate used as Customized LogicThe customized gates shown in the following figure are an example and not a unique solution
The capability register is not available for merging a Simplex TX and a Simplex RX signal into the same physical channel. The tx_cal_busy_out and rx_cal_busy_out signals share the same port. So, you should build customized gating logic to separate them.
  • The tx_cal_busy_out_en signal enables the tx_cal_busy output.
  • The rx_cal_busy_out_en signal enables the rx_cal_busy output.
  • At power up, tx_cal_busy_out_en and rx_cal_busy_out_en should be set to “1”.
  • At normal operation:
    • When the RX is calibrating, setting tx_cal_busy_out_en to “0” and rx_cal_busy_out_en to “1” disables tx_cal_busy, so the TX does not reset while RX is calibrating.
    • When the TX is calibrating, setting rx_cal_busy_out_en to “0” and tx_cal_busy_out_en to “1” disables rx_cal_busy, so the RX does not reset while TX is calibrating.
Table 300.  PMA Capability Registers for Calibration Status
Bit Description
0x281[5]

PMA channel rx_cal_busy output enable. The power up default value is 0x1.

0x1: The rx_cal_busy output and 0x281[1] are asserted high whenever PMA TX or RX calibration is running.

0x0: The rx_cal_busy output or 0x281[1] is never asserted high.

0x281[4]

PMA channel tx_cal_busy output enable. The power up default value is 0x1.

0x1: The tx_cal_busy output and 0x281[0] are asserted high whenever PMA TX or RX calibration is running.

0x0: The tx_cal_busy output or 0x281[0] is never asserted high.

0x281[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x281[1]

PMA channel rx_cal_busy active high

0x1: PMA RX calibration is running

0x0: PMA RX calibration is done

0x281[0]

PMA channel tx_cal_busy active high

0x1: PMA TX calibration is running

0x0: PMA TX calibration is done

The PMA 0x281[5:4] is used to isolate the TX and RX calibration busy status. If you want rx_cal_busy unchanged during the TX calibration, you must set 0x281[5] to 0x0 before returning the bus to PreSICE. The channel RX is not reset due to the TX calibration. If you want tx_cal_busy unchanged during the RX calibration, you must set 0x281[4] to 0x0 before returning the bus to PreSICE. The channel TX is not reset due to the RX calibration. If you accidentally write 0x00 to 0x281[5:4], tx_cal_busy and rx_cal_busy are never activated to high in the user interface. Neither of the 0x281[1:0] registers go high either.

Table 301.  ATX PLL Capability Registers for Calibration Status
Bit Description
0x280[2] PreSICE Avalon® memory-mapped interface control. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x1: PreSICE is controlling the internal configuration bus.

0x0: The user has control of the internal configuration bus.

0x280[1]

ATX PLL pll_cal_busy

0x1: ATX PLL calibration is running

0x0: ATX PLL calibration is done

Table 302.  fPLL Capability Registers for Calibration Status
Bit Description
0x280[2] PreSICE Avalon® memory-mapped interface control

0x1: PreSICE is controlling the internal configuration bus. This register is available to check who controls the bus, no matter if, separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration with PreSICE is enabled or not.

0x0: The user has control of the internal configuration bus.

0x280[1]

fPLL pll_cal_busy

0x1: fPLL calibration is running

0x0: fPLL calibration is done

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