Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.4.7. Dynamic Reconfiguration Parameters

Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device.

Each transceiver channel and PLL includes an Avalon® memory-mapped interface slave interface for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon® memory-mapped interface slave interface, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.

You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.

To enable Intel® Arria® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

  • Enable dynamic reconfiguration
  • Enable Native PHY Debug Master Endpoint
  • Enable capability registers
  • Enable control and status registers
  • Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Table 38.  Dynamic Reconfiguration
Parameter Value Description
Enable dynamic reconfiguration On/Off When you turn on this option, the dynamic reconfiguration interface is enabled.
Share reconfiguration interface On/Off When you turn on this option, the Transceiver Native PHY IP presents a single Avalon® memory-mapped interface slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:10] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel.
Enable Native PHY Debug Master Endpoint On/Off When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE On/Off When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.
Table 39.  Optional Reconfiguration Logic
Parameter Value Description
Enable capability registers On/Off Enables capability registers that provide high level information about the configuration of the transceiver channel.
Set user-defined IP identifier User-defined Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On/Off Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators On/Off Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used.
Table 40.  Configuration Files
Parameter Value Description
Configuration file prefix <prefix> Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.
Generate SystemVerilog package file On/Off When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration.
Generate C header file On/Off When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration.
Generate MIF (Memory Initialization File) On/Off When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.
Include PMA analog settings in configuration files On/Off When enabled, the IP allows you to configure the PMA analog settings that are selected in the Analog PMA settings (Optional) tab. These settings are included in your generated configuration files.
Note: You must still specify the analog settings for your current configuration using Quartus Prime Setting File (.qsf) assignments in Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog Parameter Settings chapter in the Arria® 10 Transceiver PHY User Guide for details on using the QSF assignments.
Table 41.  Configuration Profiles
Parameter Value Description
Enable multiple reconfiguration profiles On/Off When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.28
Enable embedded reconfiguration streamer On/Off Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles.
Generate reduced reconfiguration files On/Off When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files.
Number of reconfiguration profiles 1-8 Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Selected reconfiguration profile 0-7 Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile.
Store configuration to selected profile - Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Load configuration from selected profile - Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clear selected profile - Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY.
Clear all profiles - Clicking this button clears the Native PHY parameter settings for all the profiles.
Refresh selected profile - Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile.
Table 42.  Analog PMA Settings (Optional) for Dynamic Reconfiguration
Parameter Value Description
TX Analog PMA Settings
Analog Mode (Load Intel-recommended Default settings) Cei_11100_lr to xfp_9950 Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings.
Override Intel-recommended Analog Mode Default settings On/Off Enables the option to override the Intel-recommended settings for the selected TX Analog Mode for one or more TX analog parameters.
Output Swing Level (VOD) 0-31 Selects the transmitter programmable output differential voltage swing.
Pre-Emphasis First Pre-Tap Polarity

Fir_pre_1t_neg

Fir_pre_1t_pos

Selects the polarity of the first pre-tap for pre-emphasis.
Pre-Emphasis First Pre-Tap Magnitude 0-16 29 Selects the magnitude of the first pre-tap for pre-emphasis
Pre-Emphasis Second Pre-Tap Polarity

Fir_pre_2t_neg

Fir_pre_2t_pos

Selects the polarity of the second pre-tap for pre-emphasis.
Pre-Emphasis Second Pre-Tap Magnitude 0-7 30 Selects the magnitude of the second pre-tap for pre-emphasis.
Pre-Emphasis First Post-Tap Polarity

Fir_post_1t_neg

Fir_post_1t_pos

Selects the polarity of the first post-tap for pre-emphasis
Pre-Emphasis First Post-Tap Magnitude 0-25 31 Selects the magnitude of the first post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Polarity

Fir_post_2t_neg

Fir_post_2t_pos

Selects the polarity of the second post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Magnitude 0-12 32 Selects the magnitude of the second post-tap for pre-emphasis
Slew Rate Control slew_r0 to slew_r5 Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.
High-Speed Compensation Enable/Disable Enables the power-distribution network (PDN) induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.
On-Chip termination

r_r1

r_r2

Selects the on-chip TX differential termination.
RX Analog PMA settings
Override Intel-recommended Default settings On/Off Enables the option to override the Intel-recommended settings for one or more RX analog parameters
CTLE (Continuous Time Linear Equalizer) mode

non_s1_mode

S1_mode

Selects between the RX high gain mode non_s1_mode or RX high data rate mode s1_mode for the Continuous Time Linear Equalizer (CTLE).
DC gain control of high gain mode CTLE No_dc_gain to stg4_gain7 Selects the DC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode
AC Gain Control of High Gain Mode CTLE radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode when CTLE is in manual mode.
AC Gain Control of High Data Rate Mode CTLE radp_ctle_eqz_1s_sel_0 to Radp_ctle_eqz_1s_sel_15 Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high data rate mode when CTLE is in manual mode.
Variable Gain Amplifier (VGA) Voltage Swing Select radp_vga_sel_0 to radp_vga_sel_7 Selects the Variable Gain Amplifier (VGA) output voltage swing when both the CTLE and DFE blocks are in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 1 Co-efficient radp_dfe_fxtap1_0 to radp_dfe_fxtap1_127 Selects the co-efficient of the fixed tap 1 of the Decision Feedback Equalizer (DFE) when operating in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 2 Co-efficient radp_dfe_fxtap2_0 to radp_dfe_fxtap2_127 Selects the co-efficient of the fixed tap 2 of the Decision Feedback Equalizer (DFE) when operating in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 3 Co-efficient radp_dfe_fxtap3_0 to radp_dfe_fxtap3_127 Selects the co-efficient of the fixed tap 3 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 4 Co-efficient radp_dfe_fxtap4_0 to radp_dfe_fxtap4_63

Selects the co-efficient of the fixed tap 4 of the Decision Feedback Equalizer (DFE) when operating in manual mode.

Decision Feedback Equalizer (DFE) Fixed Tap 5 Co-efficient radp_dfe_fxtap5_0 to radp_dfe_fxtap5_63

Selects the co-efficient of the fixed tap 5 of the Decision Feedback Equalizer (DFE) when operating in manual mode.

Decision Feedback Equalizer (DFE) Fixed Tap 6 Co-efficient radp_dfe_fxtap6_0 to radp_dfe_fxtap6_31 Selects the co-efficient of the fixed tap 6 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 7 Co-efficient radp_dfe_fxtap7_0 to radp_dfe_fxtap7_31 Selects the co-efficient of the fixed tap 7 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 8 Co-efficient radp_dfe_fxtap8_0 to radp_dfe_fxtap8_31

Selects the co-efficient of the fixed tap 8 of the Decision Feedback Equalizer (DFE) when operating in manual mode.

Decision Feedback Equalizer (DFE) Fixed Tap 9 Co-efficient radp_dfe_fxtap9_0 to radp_dfe_fxtap9_31 Selects the co-efficient of the fixed tap 9 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 10 Co-efficient radp_dfe_fxtap10_0 to radp_dfe_fxtap10_31 Selects the co-efficient of the fixed tap 10 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 11 Co-efficient radp_dfe_fxtap11_0 to radp_dfe_fxtap11_31 Selects the co-efficient of the fixed tap 11 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
On-Chip termination R_ext0, r_r1, r_r2 Selects the on-chip RX differential termination.
Table 43.  Generation Options
Parameter Value Description
Generate parameter documentation file On/Off When you turn on this option, generation produces a Comma-Separated Value (.csv ) file with descriptions of the Transceiver Native PHY IP parameters.
28 For more information on timing closure, refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter.
29 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter Settings chapter.
30 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter Settings chapter.
31 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter Settings chapter.
32 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter Settings chapter.

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