Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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3.1.2. ATX PLL

The ATX PLL contains LC tank-based voltage controlled oscillators (VCOs). These LC VCOs have different frequency ranges to support a continuous range of operation. When driving the Transceiver directly, the ATX PLL only supports the integer mode. In cascade mode, the ATX PLL only supports fractional mode.
Figure 170. ATX PLL Block Diagram

Input Reference Clock

This is the dedicated input reference clock source for the PLL.

The input reference clock can be sourced from one of the following:

  • Dedicated reference clock pin
  • Reference clock network
  • Receiver input pin
  • Output of another PLL with PLL cascading
  • Global clock or the core clock network
The input reference clock to the dedicated reference clock pin is a differential signal. Intel recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.
Note:

Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the ATX PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria® 10 PLL reference clock?" for more details.

The ATX PLL calibration is clocked by the CLKUSR clock which must be stable and available for calibration to proceed. Refer to the Calibration section for more details about the CLKUSR clock.

Reference Clock Multiplexer

The reference clock (refclk) multiplexer selects the reference clock to the PLL from the various reference clock sources available.

N Counter

The N counter divides the refclk mux's output. The division factors supported are 1, 2, 4, and 8.

Phase Frequency Detector (PFD)

The reference clock(refclk) signal at the output of the N counter block and the feedback clock (fbclk) signal at the output of the M counter block are supplied as inputs to the PFD. The output of the PFD is proportional to the phase difference between the refclk and fbclk inputs. It is used to align the refclk signal at the output of the N counter to the feedback clock (fbclk) signal. The PFD generates an "Up" signal when the reference clock's falling edge occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's falling edge occurs before the reference clock's falling edge.

Charge Pump and Loop Filter

The PFD output is used by the charge pump and loop filter (CP and LF) to generate a control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses from the PFD into current pulses. The current pulses are filtered through a low pass filter into a control voltage that drives the VCO frequency. The charge pump, loop filter, and VCO settings determine the bandwidth of the ATX PLL.

Lock Detector

The lock detector block indicates when the reference clock and the feedback clock are phase aligned. The lock detector generates an active high pll_locked signal to indicate that the PLL is locked to its input reference clock.

Voltage Controlled Oscillator

The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The output of charge pump and loop filter serves as an input to the VCO. The output frequency of the VCO depends on the input control voltage. The output frequency is adjusted based on the output voltage of the charge pump and loop filter.

L Counter

The L counter divides the differential clocks generated by the ATX PLL. The L counter is not in the feedback path of the PLL.

M Counter

The M counter's output is the same frequency as the N counter's output. The VCO frequency is governed by the equation:

VCO freq = 2 * M * input reference clock/N

An additional divider divides the high speed serial clock output of the VCO by 2 before it reaches the M counter.

The M counter supports division factors in a continuous range from 8 to 127 in integer frequency synthesis mode and 11 to 123 in fractional mode.

Delta Sigma Modulator

The fractional mode is only supported when the ATX PLL is configured as a cascade source for OTN and SDI protocols. The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis. In fractional mode, the M value is as follows: .

M (integer) + K/2^32, where K is the Fractional multiply factor (K) in the ATX PLL IP Parameter Editor

K legal values are 1 through 2^32-1 and can only be manually entered in the ATX PLL IP Parameter Editor in Quartus Prime software.

The output frequencies can be exact when the ATX PLL is configured in fractional mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO frequency, not all desired fractional values can be achieved exactly. The lock signal is not available, when configured in fractional mode in k-precision mode (K < 0.1 or K > 0.9).

Multiple Reconfiguration Profiles

Under the ATX PLL IP Parameter Editor Dynamic Reconfiguration tab, in the Configuration Profiles section, multiple reconfiguration profiles can be enabled. This allows to create, store, and analyze the parameter settings for multiple configurations or profiles of the ATX PLL IP.

The ATX PLL IP GUI can generate configuration files (SystemVerilog, C header or MIF) for a given configuration. With the multi reconfiguration profile options enabled, the ATX PLL IP Parameter Editor can produce configuration files for all of the profiles simultaneously. In addition, by enabling the reduced reconfiguration files generation, the IP Parameter Editor produces a reduced configuration file by internally comparing the corresponding parameter settings of all the profiles and identifying the differences.

Embedded Reconfiguration Streamer

This option enables a push-button flow to reconfigure between multiple configurations or profiles. Here are the steps to follow:
  1. Multiple reconfiguration profiles creation
    • In the ATX PLL IP GUI, create configurations for each profiles using the multi-profile feature.
  2. Reconfiguration report files
    • The IP GUI generates the reconfiguration report files that contain parameter and register settings for all the selected profiles. If the reduced reconfiguration files option is selected, the IP parameter editor compares the settings between the profiles and generate reduced report files which only contain the differences.
  3. Select “Enable embedded reconfiguration streamer logic” in the GUI to generate the following:
    • Necessary HDL files to perform streaming.
    • The individual report files for each profile, an SystemVerilog package file with configuration data for all the profiles concatenated together which is used to initialize the configuration ROM
  4. Generate the ATX PLL IP and control the reconfiguration streamer using the Avalon® memory-mapped interface master.

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