Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.6.2. XAUI Supported Features

64-Bit SDR Interface to the MAC/RS

Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the XAUI PCS and the Ethernet MAC/RS. Each of the four XAUI lanes must transfer 8-bit data and a 1-bit control code at both the positive and negative edge (double data rate) of the 156.25 MHz interface clock.

Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they transfer 16-bit data and the 2-bit control code on each of the four XAUI lanes. The transfer occurs only at the positive edge (single data rate) of the 156.25 MHz interface clock.

Figure 86. Implementation of the XGMII Specification in Arria 10 Devices ConfigurationThe ATX PLL is only supported to drive the internal transceiver. The FPLL is only supported to drive xgmii_tx_clk and xgmii_rx_clk. Both the ATX PLL and the FPLL must be clocked by the same reference clock to maintain 0 ppm.


8B/10B Encoding/Decoding

Each of the four lanes in a XAUI configuration supports an independent 8B/10B encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification. 8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial data stream to five. This limit ensures DC balance as well as enough transitions for the receiver CDR to maintain a lock to the incoming data.

The XAUI PHY IP core provides status signals to indicate both running disparity and the 8B/10B code group error.

Transmitter and Receiver State Machines

In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.

The transmitter state machine performs the following functions in conformance with the 10GBASE-X PCS:

  • Encoding the XGMII data to PCS code groups
  • Converting Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R|| ordered sets

The receiver state machine performs the following functions in conformance with the 10GBASE-X PCS:

  • Decoding the PCS code groups to XGMII data
  • Converting Sync ||K||, Align ||A||, and Skip ||R|| ordered sets into Idle ||I|| ordered sets

Synchronization

The word aligner block in the receiver PCS of each of the four XAUI lanes implements the receiver synchronization state diagram shown in Figure 48-7 of the IEEE802.3-2008 specification.

The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner is synchronized to a valid word boundary.

Deskew

The lane aligner block in the receiver PCS implements the receiver deskew state diagram shown in Figure 48-8 of the IEEE 802.3-2008 specification.

The lane aligner starts the deskew process only after the word aligner block in each of the four XAUI lanes indicates successful synchronization to a valid word boundary.

The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS.

Clock Compensation

The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the remote transmitter and the local receiver. It compensates by inserting and deleting Skip ||R|| columns, depending on the ppm difference.

The clock compensation operation begins after:

  • The word aligner in all four XAUI lanes indicates successful synchronization to a valid word boundary.
  • The lane aligner indicates a successful lane deskew.

The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column for clock rate compensation.

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