Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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4.3.2.5. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model

The numbers in this list correspond to the numbers in the "Dynamic Reconfiguration of Receiver Channel During Device Operation" figure below.

  1. Assert rx_analogreset and rx_digitalreset while rx_cal_busy is low.
    1. To ensure successful assertion of rx_analogreset, wait for rx_analogreset_ack to go high. rx_analogreset_ack goes high when the TRS has successfully completed the reset request for assertion.
    2. Deassert rx_analogreset.
  2. To ensure successful deassertion of rx_analogreset, wait for rx_analogreset_ack to go low. rx_analogreset_ack goes low when the TRS has successfully completed the reset request for deassertion. 61 , 62
  3. Wait for rx_analogreset_ack to go low; then ensure rx_is_lockedtodata signal goes high after the CDR (automatic lock mode) is locked to data.
  4. After rx_is_lockedtodata goes high, wait a minimum of tLTD (minimum of 4 μs). Then deassert rx_digitalreset.
Figure 215. Dynamic Reconfiguration of Receiver Channel During Device Operation
Figure 216. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode
61 If the CDR operates in manual lock mode, step 3 and step 4 are not applicable. After rx_analogreset_ack goes low, apply the reset sequence from the "Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure below.
62 If the receiver signal detector is enabled and the CDR operates in manual lock mode, step 3 and step 4 are not applicable. After rx_analogreset_ack goes low, wait for rx_std_signaldetect to go high. When rx_std_signaldetect is high continuously for 1 μs or more, apply the reset sequence from the "Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure below.

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