Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
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2.4.5. Standard PCS Parameters

This section provides descriptions of the parameters that you can specify to customize the Standard PCS.

For specific information about configuring the Standard PCS for these protocols, refer to the sections of this user guide that describe support for these protocols.

Table 30.  Standard PCS Parameters
Note: For detailed descriptions of the optional ports that you can enable or disable, refer to the Standard PCS Ports section.
Parameter Range Description
Standard PCS/PMA interface width

8, 10, 16, 20

Specifies the data interface width between the Standard PCS and the transceiver PMA.
FPGA fabric/Standard TX PCS interface width 8, 10, 16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width. This value is determined by the current configuration of individual blocks within the Standard TX PCS datapath.
FPGA fabric/Standard RX PCS interface width 8, 10, 16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width. This value is determined by the current configuration of individual blocks within the Standard RX PCS datapath.
Enable Standard PCS low latency mode On / Off Enables the low latency path for the Standard PCS. Some of the functional blocks within the Standard PCS are bypassed to provide the lowest latency. You cannot turn on this parameter while using the Basic/Custom w/Rate Match (Standard PCS) specified for Transceiver configuration rules.
Table 31.  Standard PCS FIFO Parameters
Parameter Range Description
TX FIFO mode

low_latency

register_fifo

fast_register

Specifies the Standard PCS TX FIFO mode. The following modes are available:
  • low_latency: This mode adds 2-3 cycles of latency to the TX datapath.
  • register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI.
  • fast_register: This mode allows a higher maximum frequency (fMAX) between the FPGA fabric and the TX PCS at the expense of higher latency.
RX FIFO mode

low_latency

register_fifo

The following modes are available:
  • low_latency: This mode adds 2-3 cycles of latency to the RX datapath.
  • register_fifo: In this mode the FIFO is replaced by registers to reduce the latency through the PCS. Use this mode for protocols that require deterministic latency, such as CPRI or 1588.
Enable tx_std_pcfifo_full port On / Off Enables the tx_std_pcfifo_full port. This signal indicates when the standard TX phase compensation FIFO is full. This signal is synchronous with tx_coreclkin.
Enable tx_std_pcfifo_empty port On / Off Enables the tx_std_pcfifo_empty port. This signal indicates when the standard TX phase compensation FIFO is empty. This signal is synchronous with tx_coreclkin.
Enable rx_std_pcfifo_full port On / Off Enables the rx_std_pcfifo_full port. This signal indicates when the standard RX phase compensation FIFO is full. This signal is synchronous with rx_coreclkin.
Enable rx_std_pcfifo_empty port On / Off Enables the rx_std_pcfifo_empty port. This signal indicates when the standard RX phase compensation FIFO is empty. This signal is synchronous with rx_coreclkin.
Table 32.  Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte serializer

Disabled

Serialize x2

Serialize x4

Specifies the TX byte serializer mode for the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA serializer. The byte serializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Serialize x4 is only applicable for PCIe* protocol implementation.
Enable RX byte deserializer

Disabled

Deserialize x2

Deserialize x4

Specifies the mode for the RX byte deserializer in the Standard PCS. The transceiver architecture allows the Standard PCS to operate at double or quadruple the data width of the PMA deserializer. The byte deserializer allows the PCS to run at a lower internal clock frequency to accommodate a wider range of FPGA interface widths. Deserialize x4 is only applicable for PCIe protocol implementation.
Table 33.  8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/10B encoder On / Off When you turn on this option, the Standard PCS enables the TX 8B/10B encoder.
Enable TX 8B/10B disparity control On / Off When you turn on this option, the Standard PCS includes disparity control for the 8B/10B encoder. You can force the disparity of the 8B/10B encoder using the tx_forcedisp control signal.
Enable RX 8B/10B decoder On / Off When you turn on this option, the Standard PCS includes the 8B/10B decoder.
Table 34.  Rate Match FIFO Parameters
Parameter Range Description
RX rate match FIFO mode

Disabled

Basic 10-bit PMA width

Basic 20-bit PMA width

GbE

PIPE

PIPE 0 ppm

Specifies the operation of the RX rate match FIFO in the Standard PCS.

Rate Match FIFO in Basic (Single Width) Mode

Rate Match FIFO Basic (Double Width) Mode

Rate Match FIFO for GbE

Transceiver Channel Datapath for PIPE

RX rate match insert/delete -ve pattern (hex) User-specified 20 bit pattern Specifies the -ve (negative) disparity value for the RX rate match FIFO as a hexadecimal string.
RX rate match insert/delete +ve pattern (hex) User-specified 20 bit pattern Specifies the +ve (positive) disparity value for the RX rate match FIFO as a hexadecimal string.
Enable rx_std_rmfifo_full port On / Off Enables the optional rx_std_rmfifo_full port.
Enable rx_std_rmfifo_empty port On / Off Enables the rx_std_rmfifo_empty port.
PCI Express* Gen3 rate match FIFO mode

Bypass

0 ppm

600 ppm

Specifies the PPM tolerance for the PCI Express Gen3 rate match FIFO.
Table 35.  Word Aligner and Bitslip Parameters
Parameter Range Description
Enable TX bitslip On / Off When you turn on this option, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the tx_std_bitslipboundarysel control signal.
Enable tx_std_bitslipboundarysel port On / Off Enables the tx_std_bitslipboundarysel control signal.
RX word aligner mode

bitslip

manual (PLD controlled)

synchronous state machine

deterministic latency

Specifies the RX word aligner mode for the Standard PCS. The word aligned width depends on the PCS and PMA width, and whether or not 8B/10B is enabled.

Refer to "Word Aligner" for more information.

RX word aligner pattern length

7, 8, 10, 16, 20, 32, 40

Specifies the length of the pattern the word aligner uses for alignment.

Refer to "RX Word Aligner Pattern Length" table in "Word Aligner". It shows the possible values of "Rx Word Aligner Pattern Length" in all available word aligner modes.

RX word aligner pattern (hex) User-specified Specifies the word alignment pattern in hex.
Number of word alignment patterns to achieve sync 0-255 Specifies the number of valid word alignment patterns that must be received before the word aligner achieves synchronization lock. The default is 3.
Number of invalid words to lose sync 0-63 Specifies the number of invalid data codes or disparity errors that must be received before the word aligner loses synchronization. The default is 3.
Number of valid data words to decrement error count 0-255 Specifies the number of valid data codes that must be received to decrement the error counter. If the word aligner receives enough valid data codes to decrement the error count to 0, the word aligner returns to synchronization lock.
Enable fast sync status reporting for deterministic Latency SM On / Off When enabled, the rx_syncstatus asserts high immediately after the deserializer has completed slipping the bits to achieve word alignment. When it is not selected, rx_syncstatus asserts after the cycle slip operation is complete and the word alignment pattern is detected by the PCS (i.e. rx_patterndetect is asserted). This parameter is only applicable when the selected protocol is CPRI (Auto).
Enable rx_std_wa_patternalign port On / Off Enables the rx_std_wa_patternalign port. When the word aligner is configured in manual mode and when this signal is enabled, the word aligner aligns to next incoming word alignment pattern.
Enable rx_std_wa_a1a2size port On / Off Enables the optional rx_std_wa_a1a2size control input port.
Enable rx_std_bitslipboundarysel port On / Off Enables the optional rx_std_bitslipboundarysel status output port.
Enable rx_bitslip port On / Off Enables the rx_bitslip port. This port is shared between the Standard PCS and Enhanced PCS.
Table 36.  Bit Reversal and Polarity Inversion
Parameter Range Description
Enable TX bit reversal On / Off When you turn on this option, the 8B/10B Encoder reverses TX parallel data before transmitting it to the PMA for serialization. The transmitted TX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. During the operation of the circuit, this setting can be changed through dynamic reconfiguration.
Enable TX byte reversal On / Off When you turn on this option, the 8B/10B Encoder reverses the byte order before transmitting data. This function allows you to reverse the order of bytes that were erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS/PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules.
Enable TX polarity inversion On / Off When you turn on this option, the tx_std_polinv port controls polarity inversion of TX parallel data to the PMA. When you turn on this parameter, you also need to turn on the Enable tx_polinv port.
Enable tx_polinv port On / Off When you turn on this option, the tx_polinv input control port is enabled. You can use this control port to swap the positive and negative signals of a serial differential link, if they were erroneously swapped during board layout.
Enable RX bit reversal On / Off When you turn on this option, the word aligner reverses RX parallel data. The received RX data bit order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB. This setting can be changed through dynamic reconfiguration.

When you enable Enable RX bit reversal, you must also enable Enable rx_std_bitrev_ena port.

Enable rx_std_bitrev_ena port On / Off When you turn on this option and assert the rx_std_bitrev_ena control port, the RX data order is reversed. The normal order is LSB to MSB. The reverse order is MSB to LSB.
Enable RX byte reversal On / Off When you turn on this option, the word aligner reverses the byte order, before storing the data in the RX FIFO. This function allows you to reverse the order of bytes that are erroneously swapped. The PCS can swap the ordering of either one of the 8- or 10-bit words, when the PCS / PMA interface width is 16 or 20 bits. This option is not valid under certain Transceiver configuration rules.

When you enable Enable RX byte reversal, you must also select the Enable rx_std_byterev_ena port.

Enable rx_std_byterev_ena port On / Off When you turn on this option and assert the rx_std_byterev_ena input control port, the order of the individual 8‑ or 10‑bit words received from the PMA is swapped.
Enable RX polarity inversion On / Off

When you turn on this option, the rx_std_polinv port inverts the polarity of RX parallel data. When you turn on this parameter, you also need to enable Enable rx_polinv port.

Enable rx_polinv port On / Off When you turn on this option, the rx_polinv input is enabled. You can use this control port to swap the positive and negative signals of a serial differential link if they were erroneously swapped during board layout.
Enable rx_std_signaldetect port On / Off When you turn on this option, the optional rx_std_signaldetect output port is enabled. This signal is required for the PCI Express protocol. If enabled, the signal threshold detection circuitry senses whether the signal level present at the RX input buffer is above the signal detect threshold voltage that you specified. You can specify the signal detect threshold using a Quartus Prime Assignment Editor or by modifying the Quartus Settings File (.qsf)
Table 37.  PCIe Ports
Parameter Range Description
Enable PCIe dynamic datarate switch ports On / Off When you turn on this option, the pipe_rate, pipe_sw, and pipe_sw_done ports are enabled. You should connect these ports to the PLL IP core instance in multi-lane PCIe Gen2 and Gen3 configurations. The pipe_sw and pipe_sw_done ports are only available for multi-lane bonded configurations.
Enable PCIe pipe_hclk_in and pipe_hclk_out ports On / Off When you turn on this option, the pipe_hclk_in, and pipe_hclk_out ports are enabled. The pipe_hclk_in port must be connected to the PLL IP core instance for the PCI Express configurations. The pipe_hclk_out port can be left floating when you connect tx_clkout to the MAC clock input.
Enable PCIe Gen3 analog control ports On / Off When you turn on this option, the pipe_g3_txdeemph and pipe_g3_rxpresenthint ports are enabled. You can use these ports for equalization for Gen3 configurations.
Enable PCIe electrical idle control and status ports On / Off When you turn on this option, the pipe_rx_eidleinfersel and pipe_rx_elecidle ports are enabled. These ports are used for PCI Express configurations.
Enable PCIe pipe_rx_polarity port On / Off When you turn on this option, the pipe_rx_polarity input control port is enabled. You can use this option to control channel signal polarity for PCI Express configurations. When the Standard PCS is configured for PCIe, the assertion of this signal inverts the RX bit polarity. For other Transceiver configuration rules the optional rx_polinv port inverts the polarity of the RX bit stream.

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