Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
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1.2.1. Transceiver Bank Architecture

The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's high speed serial transceivers.

Each transceiver bank includes six transceiver channels in all devices except for the devices with 66 transceiver channels. Devices with 66 transceiver channels have both six channel and three channel transceiver banks. The uppermost transceiver bank on the left and the right side of these devices is a three channel transceiver bank. All other devices contain only six channel transceiver banks.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

Figure 12. Three-Channel GX Transceiver Bank Architecture


Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
Figure 13. Six-Channel GX Transceiver Bank Architecture


Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
Figure 14.  GT Transceiver Bank ArchitectureIn the GT device, the transceiver banks GXBL1E, GXBL1G, and GXBL1H include GT channels.


Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.
Figure 15.  GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H
Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter.

The transceiver channels perform all the required PHY layer functions between the FPGA fabric and the physical medium. The high speed clock required by the transceiver channels is generated by the transceiver PLLs. The master and local clock generation blocks (CGBs) provide the necessary high speed serial and low speed parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.

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