Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.5.4.1. Register Map

You can access the 16-bit/32-bit configuration registers via the Avalon® memory-mapped interface.

Table 157.  Register Map
Address Range Usage Bit Configuration
0x00 : 0x1F 1000BASE-X/SGMII 16 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE-T)
0x400 : 0x41F USXGMII 32 10M/100M/1G/2.5G/5G/10G (USXGMII)
0x461 Serial Loopback 32 10M/100M/1G/2.5G/5G/10G (USXGMII)

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