Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

5.2.2.10. Enhanced PCS RX FIFO

The Enhanced PCS RX FIFO is designed to compensate for the phase, clock, or phase and clock difference between the receiver channel PCS and the FPGA fabric. It can operate as a phase-compensation, clock-compensation, elastic buffer, or a deskew FIFO in Interlaken mode. The RX FIFO has a width of 74 bits and a depth of 32 words for all protocols.

The RX FIFO supports the following modes:

  • Phase Compensation mode
  • Register mode
  • Interlaken mode (deskew FIFO)
  • 10GBASE-R mode (clock compensation FIFO)
  • Basic mode (elastic buffer FIFO)

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