Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.7.2.2.4. Gen3 Clock Compensation

Enable this mode from the Parameter Editor when using the Gen3 PIPE transceiver configuration rule.

To accommodate PCIe* protocol requirements and to compensate for clock frequency differences of up to ±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. If the rate match FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts a SKP character at the start of the next available SKP ordered set. The pipe_rx_status [2:0] signal indicates FIFO full, empty, insertion and deletion.
Note: Refer to the Gen1 and Gen2 Clock Compensation section for waveforms.

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