Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2

This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Table 90.  General and Datapath OptionsThe first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
Parameter Value
Message level for rule violations

error

warning

Transceiver configuration rules

GbE (for GbE)

GbE 1588 (for GbE with IEEE 1588v2)

Transceiver mode

TX/RX Duplex

TX Simplex

RX Simplex

Number of data channels 1 to 96
Data rate 1250 Mbps
Enable datapath and interface reconfiguration

On/Off

Enable simplified data interface

On/Off

Table 91.  TX PMA Parameters
Parameter Value
TX channel bonding mode Not bonded
TX local clock division factor 1, 2, 4, 8
Number of TX PLL clock inputs per channel 1, 2, 3, 4
Initial TX PLL clock input selection 0 to 3
Enable tx_pma_clkout port

On/Off

Enable tx_pma_div_clkout port

On/Off

tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port

On/Off

Enable tx_pma_qpipullup port (QPI)

On/Off

Enable tx_pma_qpipulldn port (QPI)

On/Off

Enable tx_pma_txdetectrx port (QPI)

On/Off

Enable tx_pma_rxfound port (QPI)

On/Off

Enable rx_seriallpbken port

On/Off

Table 92.  RX PMA Parameters
Parameter Value
Number of CDR reference Clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock frequency Select legal range defined by the Quartus Prime software
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual
DFE adaptation mode disabled
Number of fixed dfe taps N/A
Enable rx_pma_clkout port

On/Off

Enable rx_pma_div_clkout port

On/Off

rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_iqtxrx_clkout port

On/Off

Enable rx_pma_clkslip port

On/Off

Enable rx_pma_qpipulldn port (QPI)

Off

Enable rx_is_lockedtodata port

On/Off

Enable rx_is_lockedtoref port

On/Off

Enable rx_set_locktodata and rx_set_locktoref ports

On/Off

Enable rx_seriallpbken port

On/Off

Enable PRBS verifier control and status ports

On/Off

Table 93.  Standard PCS Parameters
Parameters Value
Standard PCS / PMA interface width 10
FPGA fabric / Standard TX PCS interface width 8
FPGA fabric / Standard RX PCS interface width 8
Enable Standard PCS low latency mode Off
TX FIFO mode

low latency (for GbE)

register_fifo (for GbE with IEEE 1588v2)

RX FIFO mode

low latency (for GbE)

register_fifo (for GbE with IEEE 1588v2)

Enable tx_std_pcfifo_full port

On/Off

Enable tx_std_pcfifo_empty port

On/Off

Enable rx_std_pcfifo_full port

On/Off

Enable rx_std_pcfifo_empty port

On/Off

TX byte serializer mode Disabled
RX byte deserializer mode Disabled
Enable TX 8B/10B encoder

On

Enable TX 8B/10B disparity control

On/Off

Enable RX 8B/10B decoder

On

RX rate match FIFO mode

gige (for GbE)

disabled (for GbE with IEEE 1588v2)

RX rate match insert / delete -ve pattern (hex)

0x000ab683 (/K28.5/D2.2/) (for GbE)

0x00000000 (disabled for GbE with IEEE 1588v2)

RX rate match insert / delete +ve pattern (hex)

0x000a257c (/K28.5/D16.2/) (for GbE)

0x00000000 (disabled for GbE with IEEE 1588v2)

Enable rx_std_rmfifo_full port

On/Off

(option disabled for GbE with IEEE 1588v2)

Enable rx_std_rmfifo_empty port

On/Off

(option disabled for GbE with IEEE 1588v2)

PCI Express* Gen3 rate match FIFO mode Bypass
Enable TX bit slip Off
Enable tx_std_bitslipboundarysel port

On/Off

RX word aligner mode Synchronous state machine
RX word aligner pattern length 7
RX word aligner pattern (hex) 0x000000000000007c (Comma) (for 7-bit aligner pattern length), 0x000000000000017c (/K28.5/) (for 10-bit aligner pattern length)
Number of word alignment patterns to achieve sync 3
Number of invalid data words to lose sync 3
Number of valid data words to decrement error count 3
Enable fast sync status reporting for deterministic latency SM

On/Off

Enable rx_std_wa_patternalign port Off
Enable rx_std_wa_a1a2size port Off
Enable rx_std_bitslipboundarysel port Off
Enable rx_bitslip port Off
Enable TX bit reversal Off
Enable TX byte reversal Off
Enable TX polarity inversion

On/Off

Enable tx_polinv port

On/Off

Enable RX bit reversal Off
Enable rx_std_bitrev_ena port Off
Enable RX byte reversal Off
Enable rx_std_byterev_ena port Off
Enable RX polarity inversion

On/Off

Enable rx_polinv port

On/Off

Enable rx_std_signaldetect port

On/Off

All options under PCIe* Ports Off

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