Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow

Use the Native PHY IP core or PLL IP core guided reconfiguration flow to perform dynamic reconfiguration when you need to change multiple parameters or parameters in multiple addresses for the transceiver channel or PLL. You can use this flow to change data rates, change clock divider values, or switch from one PCS datapath to another. You must generate the required configuration files for the base and modified Transceiver Native PHY IP core or PLL IP core configurations.

The configuration files contain addresses and bit values of the corresponding configuration. Compare the differences between the base and modified configuration files. The differences between these files indicate the addresses and bit values that must change to switch from one configuration to another. Perform read-modify-writes for the bit values that are different from the base configuration to obtain the modified configuration.

To perform dynamic reconfiguration using the IP Guided Reconfiguration Flow:

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Perform a read-modify-write to all addresses and bit values that are different from the base configuration.
  3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.
Note: If reconfiguration involved data rate or protocol mode changes, you may need to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA Analog Parameters section for more details.

The bit values that must be changed to obtain the new configuration may span across multiple addresses, such as when switching between Standard, Enhanced, and PCS Direct data paths. It is difficult to manually compare these values for the base and modified configurations and then build logic to stream the different values in the modified configuration. You can use the multiple profiles feature of the Native PHY/ATX PLL IP cores to store the parameter settings (MIF configuration file) to memory. With the configuration content saved, you can read from the memory and write the content to the target channel for reconfiguration. Optionally, you can also use the embedded reconfiguration streamer feature of the Native PHY/ATX PLL IP cores, which includes the logic to store the individual profile information and logic to perform streaming. Using the embedded reconfiguration streamer, you can reduce the number of read-modify-write operations to obtain the modified configuration.

To perform dynamic reconfiguration using the Embedded Reconfiguration Streamer:

  1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic Reconfiguration.
  2. Perform a read-modify-write to address x340 with the desired profile select, broadcast bit (applicable for Native PHY only), and configuration load bit set accordingly. For example, to stream profile 1 to a channel, perform a read-modify-write to bits x340[2:0] with 3’b001, bit x340[6] with 1’b0 to disable broadcasting, and bit x340[7] with 1’b1 to initiate streaming.
  3. Poll the streamer busy bit at address x341 (x341[0]) at regular intervals. When the busy bit is 1’b0, the reconfiguration is complete.
  4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration.
Note: If reconfiguration involved data rate or protocol mode changes, you may need to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA Analog Parameters section for more details.
Figure 274. Timing Diagram for Embedded Streamer Reconfiguration

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