Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

7.2.2. Transceiver Channel Calibration Registers

Table 297.  Transceiver Channel PMA Calibration Registers
Bit PMA Calibration Enable Register Offset Address 0x100
0 Reserved
1 PMA RX calibration enable
2 Reserved
3 Reserved
4 Reserved
5 PMA TX calibration enable
6 Write 1'b0 to 0x100 [6] when you enable any PMA channel calibration to ensure adaptation triggering request is disable.
7 Reserved

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