Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

7.5.1. ATX PLL Recalibration

When you use the ATX PLL in your application, and it requires a line rate or clock frequency change, you must recalibrate the ATX PLL after you have made the changes.

Follow these steps to recalibrate the ATX PLL:

  1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0].
  2. Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon® memory-mapped interface control 0x280[2]=0x0.
  3. To calibrate the ATX PLL, doing Read-Modify-Write 0x1 to bit[0] of address 0x100 of the ATX PLL.
  4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0].
  5. Periodically check the *cal_busy output signals or read the capability registers 0x280[1] to check *cal_busy status until calibration is complete.
Note: If you are recalibrating your ATX PLL and have adjacent ATX PLL used on the same side of the device, follow the ATX PLL-to-ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.