Intel® Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.5.4. Speed Detection Parameters

Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
Table 133.  Speed Detection
Parameter Name Options Description
Enable automatic speed detection On

Off

When you turn this option On, the core includes the Sequencer block that sends reconfiguration requests to detect 1G or 10GbE when the Auto Negotiation block is not able to detect AN data.

Avalon‑MM clock frequency 100-162 MHz Specifies the clock frequency for phy_mgmt_clk.
Link fail inhibit time for 10Gb Ethernet 504 ms Specifies the time before link_status is set to FAIL or OK. A link fails if the link_fail_inhibit_time has expired before link_status is set to OK. The legal range is 500-510 ms. For more information, refer to "Clause 73 Auto Negotiation for Backplane Ethernet" in IEEE Std 802.3ap-2007.
Link fail inhibit time for 1Gb Ethernet 40-50 ms Specifies the time before link_status is set to FAIL or OK . A link fails if the link_fail_inhibit_time has expired before link_status is set to OK. The legal range is 40-50 ms.
Enable PCS-Mode port On

Off

Enables or disables the PCS-Mode port.

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