Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents

2.7.12. How to Place Channels for PIPE Configurations

Instead of the fitter or software model, the hardware dictates all the placement restrictions. The restrictions are listed below:

  • The channels must be contiguous for bonded designs.
  • The master CGB is the only way to access x6 lines and must be used in bonded designs. The local CGB cannot be used to route clock signals to slave channels because the local CGB does not have access to x6 lines.
  • When implementing a Gen3-capable PIPE configuration in a -2 or -3 core speed grade, you cannot place the Logical PCS Master Channel in a location adjacent to the Hard IP (HIP).
  • Non PCIe*-Channels that are placed next to active banks with PIPE interfaces that are Gen3 capable have the following restrictions
    • When VCCR_GXB and VCCT_GXB are set to 1.03 V or 1.12 V, the maximum data rate supported for the non-PCIe channels in those banks is 12.5 Gbps for chip-to-chip applications. These channels cannot be used to drive backplanes or for GT rates.
    • When VCCR_GXB and VCCT_GXB are set to 0.95 V, the non-PCIe channels in those banks cannot be used.

For channel placement guidelines when using Arria 10 Hard IP for PCIe, refer to the PCIe User Guide.

For ATX PLL placement restrictions, refer to the section "Transmit PLL Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.

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