22.214.171.124. ATX Reference Clock Switching
Before initiating a reference clock switch, ensure that your ATX PLL instance defines more than one reference clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during ATX PLL parameterization.
The following table shows the addresses and bits for switching between ATX PLL reference clock inputs. The number of exposed pll_refclk ports varies according to the number of reference clocks you specify. Use the ATX PLL reconfiguration interface for this operation.
|Transceiver ATX PLL Port||Description||Address||Bits|
Represents logical refclk0. Lookup register x113[7:0] stores the mapping from logical refclk0 to the physical refclk.
|0x113 (Lookup Register)||[7:0]|
Represents logical refclk1. Lookup register x114[7:0] stores the mapping from logical refclk1 to the physical re