Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents ATX Reference Clock Switching

You can use the reconfiguration interface on the ATX PLL instance to specify which reference clock source drives the ATX PLL. The ATX PLL supports clocking up to five different reference clock sources. The flow to select between the different reference clock sources is independent of the number of transmitter PLLs specified in the Parameter Editor.

Before initiating a reference clock switch, ensure that your ATX PLL instance defines more than one reference clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during ATX PLL parameterization.

The following table shows the addresses and bits for switching between ATX PLL reference clock inputs. The number of exposed pll_refclk ports varies according to the number of reference clocks you specify. Use the ATX PLL reconfiguration interface for this operation.

Table 269.  Register Map for Switching ATX PLL Reference Clock Inputs
Transceiver ATX PLL Port Description Address Bits

Represents logical refclk0. Lookup register x113[7:0] stores the mapping from logical refclk0 to the physical refclk.

0x113 (Lookup Register) [7:0]

Represents logical refclk1. Lookup register x114[7:0] stores the mapping from logical refclk1 to the physical re