Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Document Table of Contents 1G/10GbE PHY Functional Description

Figure 73. 1G/10GbE PHY Block Diagram

Standard and Enhanced PCS Datapaths

The Standard PCS and PMA inside the Native PHY are configured as the Gigabit Ethernet PHY. The Enhanced PCS and PMA inside the Native PHY are configured as the 10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more details.


The Sequencer controls the start-up sequence of the PHY IP, including reset and power-on. It selects which PCS (1G or 10G) and PMA interface is active. The Sequencer interfaces to the reconfiguration block to request a change from one data rate to the other data rate.


The GigE PCS includes the GMII interface and Clause 37 auto negotiation and SGMII functionality.

Soft Enhanced PCS FIFO for IEEE 1588v2

In IEEE 1588v2 mode, the enhanced PCS FIFOs for both TX and RX are constructed in soft IP to include the latency information via the latency adjustment ports. For more information about the required latency information in the MAC as part of the Precision Time Protocol implementation, refer to the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide.

Reconfiguration Block

The reconfiguration logic performs the Avalon® memory-mapped interface writes to the PHY for both PCS and PMA reconfiguration. The following figure shows the details of the reconfiguration blocks. The Avalon® memory-mapped interface master accepts requests from the PMA or PCS controller. It performs the Read-Modify-Write or Write commands using the Avalon® memory-mapped interface. The PCS controller receives data rate change requests from the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and PCS.

Figure 74. Reconfiguration Block DetailsThe 1G/10GbE PHY IP core is very flexible. For example, you can configure it with or without IEEE 1588v2, and with or without FEC in the enhanced PCS datapath.

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