Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 3/28/2022
Public
Document Table of Contents

2.6.4.3. 1G/10GbE PHY Functional Description

Figure 73. 1G/10GbE PHY Block Diagram

Standard and Enhanced PCS Datapaths

The Standard PCS and PMA inside the Native PHY are configured as the Gigabit Ethernet PHY. The Enhanced PCS and PMA inside the Native PHY are configured as the 10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more details.

Sequencer

The Sequencer controls the start-up sequence of the PHY IP, including reset and power-on. It selects which PCS (1G or 10G) and PMA interface is active. The Sequencer interfaces to the reconfi