Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents
Give Feedback Capability Registers

The capability registers provide high level information about the transceiver channel and PLL configuration.

The capability registers capture a set of chosen capabilities of the PHY that cannot be reconfigured. The following capability registers are available for the Native PHY IP core.

Table 284.  Capability Registers for the Native PHY IP Core
Address Type Name Description
0x200[7:0] RO IP Identifier Unique identifier for the Native PHY IP instance.
0x204[0] RO Status Register Enabled Indicates whether the status registers have been enabled. 1'b1 indicates that the status registers are enabled.
0x205[0] RO Control Register Enabled