Arria® 10 Transceiver PHY User Guide

ID 683617
Date 4/01/2024
Public
Document Table of Contents

7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers

Table 296.   Avalon® Memory-Mapped Interface Arbitration Registers
Bit Offset Address Description
[0] 0x063 This bit arbitrates the control of Avalon® memory-mapped interface.
  • Set this bit to 0 to request control of the internal configuration bus by user.
  • Set this bit to 1 to pass the internal confi