Intel® Arria® 10 Transceiver PHY User Guide

ID 683617
Date 9/15/2023
Document Table of Contents

7.6. Calibration Revision History

Document Version Changes
2018.09.24 Made the following change:
  • Noted that PCIe* requires power-up calibration, and the power-up calibration requires a reference clock.
2018.06.15 Made the following change:
  • Added a footnote: CDR and CMU PLL calibration are part of RX PMA calibration.
2017.11.06 Made the following changes:
  • Updated the flow of "User Recalibration" topic.
  • Updated "
    • In order to trigger user re-calibration:
      • Write 0x01 to offset address 0x000 [7:0], user re-calibration has to request through offset address 0x100.
    • In order to trigger DFE adaptation:
      • Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to enable through 0x100[6].
    • If you no longer need to use the internal reconfiguration bus:
      • Write 0x03 to offset address 0x000 [7:0].
    " in the "Reconfiguration Interface and Arbitration with PreSICE Calibration Engine" topic.
  • Updated "You must also set the 0x100 [6] to 0x0 when you enable any PMA channel calibration to ensure adaptation triggering is disabled." in "User Recalibration" topic.
  • Updated "PMA Calibration Enable Register Offset Address 0x100" to "Write 1'b0 to 0x100 [6] when you enable any PMA